数字逻辑与数字系统（VHDL）动态扫描数码显示器

2019-04-14 21:32发布

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分析

做一个动态扫描数码显示器 一共需要三个部件： 模八计数器、8选一数据选择器、7段译码器

模八计数器

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith; Entity m8 is port(en,clr,clk:in std_logic; q:out std_logic_vector(2 downto 0) ); end m8; architecture s_m8 of m8 is signal qcl:std_logic_vector(2 downto 0); begin process(en,clr,clk) if(clr='0')then qcl<="000"; elseif(clk'event and clk='1')then if(en='1')then if(qcl="111")then qcl<="000"; else qcl<=qcl+'1'; end if; end if; end if; q<=qcl; end process; end s_m8;

8选一数据选择器

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith; Entity xz8 is port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic_vector(3 downto 0); sel:in std_logic_vector(2 downto 0); q:out std_logic_vector(3 downto 0) ); end xz8; architecture s_xz8 of xz8 is signal qc:std_logic_vector(2 downto 0); begin process(d0,d1,d2,d3,d4,d5,d6,d7,sel) begin case sel is when "000"=>qc<=d0; when "001"=>qc<=d1; when "010"=>qc<=d2; when "011"=>qc<=d3; when "100"=>qc<=d4; when "101"=>qc<=d5; when "110"=>qc<=d6; when "111"=>qc<=d7; end case; end process; end s_xz8;

7段译码器

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith; Entity ymq is port(d:in std_logic_vector(3 downto 0); f:out std_logic_vector(6 downto 0) ); end ymq; architecture s_ymq of ymq is begin process(d) begin case d is when "0000"=>f<="0111111"; when "0001"=>f<="0000110"; when "0010"=>f<="1011011"; when "0011"=>f<="1001111"; when "0100"=>f<="1100110"; when "0101"=>f<="1101101"; when "0110"=>f<="1111101"; when "0111"=>f<="0100111"; when "1000"=>f<="1111111"; when "1001"=>f<="1101111"; when others=>f<="XXXXXXX"; end case; end process; end s_ymq;PS： 时间太久想不起更具体的了= =就酱暂且记录一下

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