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参考：PIC32MX Datasheet
关于 PIC32中的coprocessor0，即CP0，我们称之为系统控制协处理器（SYSTEM CONTROL COPROCESSOR ）以下摘录自PIC32数据手册：
3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS® architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e®, is also available by accessing the CP0 registers, listed in Table 3-2.
3.2.3 系统控制协处理器 (CP0) 在 MIPS 构架中,CP0 负责处理虚拟地址到物理地址的转换、异常控制系统、处理器的诊断功能、工作模式 (内核、用户和调试)以及允许或禁止中断。通过访问 CP0 寄存器也可以得到表3-2 中列出的配置信息(例如显示MIPS16e等选项)。
关于 PIC32中的coprocessor0，即CP0，我们称之为系统控制协处理器（SYSTEM CONTROL COPROCESSOR ）以下摘录自PIC32数据手册：
3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS® architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e®, is also available by accessing the CP0 registers, listed in Table 3-2.
3.2.3 系统控制协处理器 (CP0) 在 MIPS 构架中,CP0 负责处理虚拟地址到物理地址的转换、异常控制系统、处理器的诊断功能、工作模式 (内核、用户和调试)以及允许或禁止中断。通过访问 CP0 寄存器也可以得到表3-2 中列出的配置信息(例如显示MIPS16e等选项)。