芯片PIC18F4553 (MCHP) -- 8位单片机， 汇编开发单片机

2019-04-15 14:49发布

站内文章 / PIC单片机
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; ; TEST-GPIO ; ; FileName: main.S ; Dependencies: p18f4553.inc ; ; Processor: PIC18F4553 ; ; Complier: GPASM ; ; Company: xxx ; ; Date: 2012/03/21 ; ; Author: Perry.Peng@xxx.com ; ; just do a demonstration of PIC18F4553. ; ; Features used: ; - GPIO ; - Timer1 ; ; Description: ; demo program. ; ; Notes: ; - ; nolist list r=dec, f=inhx32 list n=0; suppress list file page breaks list ST=off; suppress list file symbol table errorlevel -302 ; suppress message 302 from list file include "p18f4553.inc" ; --------------------------------------------------------------------- ; Configuration Bits ; --------------------------------------------------------------------- CONFIG PLLDIV = 3 ; PLL Prescaler Selection bits CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits CONFIG USBDIV = 1 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) CONFIG FOSC = HSPLL_HS ; Oscillator Selection bits CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit CONFIG DEBUG = ON ; Background Debugger Enable bit CONFIG XINST = OFF ; Extended Instruction Set Enable bit CONFIG MCLRE = ON ; MCLR Pin Enable bit CONFIG PWRT = OFF ; MCLR Pin Enable bit CONFIG WDT = OFF ; WDT disabled. CONFIG WDTPS = 128 ; Watchdog Timer Postscale Select bits(1 to 32768). CONFIG VREGEN = OFF ; USB voltage regulator disabled. CONFIG CCP2MX = OFF ; CCP2 input/output is multiplexed with RB3. CONFIG PBADEN = OFF ; PORTB<4:0> pins are configured as digital I/O on Reset CONFIG LVP = ON ; PORTB<4:0> pins are configured as ; Instructs gpasm that it should generate an error if there is any ; use of the given RAM locations. STATUS equ 0xfd8 WREG equ 0xfe8 FSR1L equ 0xfe1 FSR2L equ 0xfd9 POSTINC1 equ 0xfe6 POSTDEC1 equ 0xfe5 PREINC1 equ 0xfe4 PLUSW2 equ 0xfdb ;---------------------------------------------------------------------- ; Variables ;---------------------------------------------------------------------- .data udata .registers udata_ovr 0x0000 r0x00 res 1 r0x01 res 1 r0x02 res 1 r0x03 res 1 r0x04 res 1 r0x05 res 1 ;---------------------------------------------------------------------- ; Program Memory ;---------------------------------------------------------------------- org 0x0000 ; Reset vector nop goto sysboot org 0x0008 ; Low-priority vector retfie ; org 0x0018 ; High-priority interrupt vector ; nop ; retfie org 0x00020 ; Start of Program space sysboot call SystemClockInit movlw 0xaa movwf LATD ; clear PORTB output latch bsf PORTE, RDPU ; PORTD pull-ups are enabled by individual port latch values movlw 0xf8 ; set PORTB[0:2] as outputs movwf TRISD clrf BAUDCON clrf SPBRGH movlw 0x4e ; ((48MHz / 9600) / 64) - 1 movwf SPBRG movlw 0x20 movwf TXSTA movlw 0x90 movwf RCSTA clrf TMR0L clrf TMR0H bcf INTCON, TMR0IF bcf T0CON, T0PS0 bsf T0CON, T0PS1 bsf T0CON, T0PS2 bcf T0CON, PSA bcf T0CON, T0SE bcf T0CON, T0CS bsf T0CON, T08BIT ; 16bit mode. bsf T0CON, TMR0ON Main btg LATD, 0 btg LATD, 1 btg LATD, 2 movlw 0x41 call putc movlw 0x42 call putc movlw 0x43 call putc movlw 0x0d call putc movlw 0x0a call putc btfss INTCON, TMR0IF goto $ - 1 bcf INTCON, TMR0IF goto Main ; do it all over again ;---------------------------------------------------------------------- ; a delay of 98.57mS Delay movlw 0x80 movwf r0x01 ; preset clrf r0x00 ; clear counter Delay1 decfsz r0x00, 1 ; decrement counter bra Delay1 ; back to top of loop decfsz r0x01, 1 ; decrement counter bra Delay1 ; back to top of loop return putc: btfss TXSTA, TRMT bra $ - 1 movwf TXREG return puts: return OpenUart: clrf BAUDCON clrf SPBRGH movlw 0x4e ; ((48MHz / 9600) / 64) - 1 movwf SPBRG movlw 0x20 movwf TXSTA movlw 0x90 movwf RCSTA return EnableInterrupt: ; INTCON ; R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x ; GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF ; bit7 6 5 4 3 2 1 0 ; ; GIE/GIEH: Global Interrupt Enable bit ; When IPEN = 0: ; 1= Enables all unmasked interrupts ; 0= Disables all interrupts ; When IPEN = 1: ; 1= Enables all high-priority interrupts ; 0= Disables all interrupts ; PEIE/GIEL: Peripheral Interrupt Enable bit ; When IPEN = 0: ; 1= Enables all unmasked peripheral interrupts ; 0= Disables all peripheral interrupts ; When IPEN = 1: ; 1= Enables all low-priority peripheral interrupts (if GIE/GIEH = 1) ; 0= Disables all low-priority peripheral interrupts ; TMR0IE:TMR0 Overflow Interrupt Enable bit ; 1= Enables the TMR0 overflow interrupt ; 0= Disables the TMR0 overflow interrupt ; INT0IE:INT0 External Interrupt Enable bit ; 1= Enables the INT0 external interrupt ; 0= Disables the INT0 external interrupt ; RBIE:RB Port Change Interrupt Enable bit ; 1= Enables the RB port change interrupt ; 0= Disables the RB port change interrupt ; TMR0IF:TMR0 Overflow Interrupt Flag bit ; 1= TMR0 register has overflowed (must be cleared in software) ; 0= TMR0 register did not overflow ; INT0IF:INT0 External Interrupt Flag bit ; 1= The INT0 external interrupt occurred (must be cleared in software) ; 0 = The INT0 external interrupt did not occur ; RBIF:RB Port Change Interrupt Flag bit ; 1= At least one of the RB7:RB4 pins changed state (must be cleared in software) ; 0 = None of the RB7:RB4 pins have changed state ; ; INTCON2 ; R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 ; RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP ; bit7 6 5 4 3 2 1 0 ; ; ; INTCON3 ; R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ; INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF ; bit7 6 5 4 3 2 1 0 bcf INTCON2, 2 bsf INTCON, 5 bsf INTCON, 6 bsf INTCON, 7 return Timer0Init: ; T0CON register ; R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ; TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 ; bit7 6 5 4 3 2 1 0 ; ; TMR0ON: Timer0 On/Off Control bit ; 1= Enables Timer0 ; 0= Stops Timer0 ; ; T08BIT: Timer0 8-Bit/16-Bit Control bit ; 1= Timer0 is configured as an 8-bit timer/counter ; 0= Timer0 is configured as a 16-bit timer/counter ; ; T0CS: Timer0 Clock Source Select bit ; 1= Transition on T0CKI pin ; 0= Internal instruction cycle clock (CLKO) ; ; T0SE: Timer0 Source Edge Select bit ; 1= Increment on high-to-low transition on T0CKI pin ; 0= Increment on low-to-high transition on T0CKI pin ; ; PSA: Timer0 Prescaler Assignment bit ; 1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. ; 0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. ; ; T0PS2:T0PS0: Timer0 Prescaler Select bits ; 111= 1:256 Prescale value ; 110= 1:128 Prescale value ; 101= 1:64 Prescale value ; 100= 1:32 Prescale value ; 011= 1:16 Prescale value ; 010= 1:8 Prescale value ; 001= 1:4 Prescale value ; 000= 1:2 Prescale value clrf TMR0L clrf TMR0H bcf INTCON, TMR0IF bsf T0CON, T0PS0 bsf T0CON, T0PS1 bsf T0CON, T0PS2 bcf T0CON, PSA bcf T0CON, T0SE bcf T0CON, T0CS bsf T0CON, T08BIT ; 16bit mode. bsf T0CON, TMR0ON return SystemClockInit: ; OSCCON register ; R/W-0 R/W-1 R/W-0 R/W-0 R R-0 R/W-0 R/W-0 ; IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 ; bit7 6 5 4 3 2 1 0 ; ; IDLEN: Idle Enable bit ; 1= Device enters Idle mode on SLEEP instruction ; 0= Device enters Sleep mode on SLEEP instruction ; ; IRCF2:IRCF0: Internal Oscillator Frequency Select bits ; 111= 8 MHz (INTOSC drives clock directly) ; 110= 4 MHz ; 101= 2 MHz ; 100= 1 MHz (Default output frequency of INTOSC on Reset.) ; 011= 500 kHz ; 010= 250 kHz ; 001= 125 kHz ; 000= 31 kHz (from either INTOSC/256 or INTRC directly) ; ; OSTS:Oscillator Start-up Time-out Status bit (Depends on the state of the IESO Configuration bit) ; 1= Oscillator Start-up Timer time-out has expired; primary oscillator is running ; 0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready ; ; IOFS:INTOSC Frequency Stable bit ; 1= INTOSC frequency is stable ; 0= INTOSC frequency is not stable ; ; SCS1:SCS0:System Clock Select bits ; 1x= Internal oscillator ; 01= Timer1 oscillator ; 00= Primary oscillator bcf OSCCON, SCS0 bcf OSCCON, SCS1 bsf OSCCON, IRCF0 bsf OSCCON, IRCF1 bsf OSCCON, IRCF2 bcf OSCCON, IDLEN ; btfss OSCCON, 2 ; bra $ - 1 return ;---------------------------------------------------------------------- ; End of program ;---------------------------------------------------------------------- end

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