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File > New > CodeWarrior BareBoard Project Wizard > Download SRAM
Download RAM不能工作,确定是电路板改了DDR的电路,所以需要修改配置,根据参考(未验证),
#######################################
# DDRC INITIALIZATION
#######################################
#DDR_SDRAM_CFG
#mem [CCSR 0x2110] = 0x470c0000
mem [CCSR 0x2110] = 0x47140008
#CS0_BNDS
#mem [CCSR 0x2000] = 0x0000001F
mem [CCSR 0x2000] = 0x00000007
#CS0_CONFIG
#mem [CCSR 0x2080] = 0x80014302
mem [CCSR 0x2080] = 0x80014102
#TIMING_CFG_0
mem[CCSR 0x2104] = 0x00110004
#TIMING_CFG_1
#mem [CCSR 0x2108] = 0x5d59e544
mem [CCSR 0x2108] = 0x6f6b8644
#TIMING_CFG_2
#mem [CCSR 0x210c] = 0x0fa890cd
mem [CCSR 0x210c] = 0x0fa888cf
#TIMING_CFG_3
#mem [CCSR 0x2100] = 0x00010000
mem [CCSR 0x2100] = 0x00030000
#DDR_SDRAM_CFG_2
#mem [CCSR 0x2114] = 0x04401000
mem [CCSR 0x2114] = 0x24401000
#DDR_SDRAM_MODE
#mem [CCSR 0x2118] = 0x00441210
mem [CCSR 0x2118] = 0x00441420
#DDR_SDRAM_MODE_2
mem[CCSR 0x211C] = 0x00000000
#DDR_SDRAM_MD_CNTL
mem[CCSR 0x2120] = 0x00000000
#DDR_SDRAM_INTERVAL
#mem [CCSR 0x2124] = 0x0a280000
mem [CCSR 0x2124] = 0x0c300100
#DDR_DATA_INIT
mem[CCSR 0x2128] = 0xDEADBEEF
#DDR_SDRAM_CLK_CNTL
mem[CCSR 0x2130] = 0x03000000
#TIMING_CFG_4
mem[CCSR 0x2160] = 0x00000001
#TIMING_CFG_5
#mem [CCSR 0x2164] = 0x03402400
mem [CCSR 0x2164] = 0x02401400
#DDR_ZQ_CNTL
mem[CCSR 0x2170] = 0x89080600
#DDR_WRLVL_CNTL
mem[CCSR 0x2174] = 0x8675f608
#ERR_INT_EN
mem[CCSR 0x2E48] = 0x00000000
#DDR_ERR_SBE
mem[CCSR 0x2E58] = 0x00000000
#DDR_CDR1
mem[CCSR 0x2B28] = 0x00000000
#DDR_CDR2
mem[CCSR 0x2B2C] = 0x00000000
#delaybefore enable
wait500
#DDR_SDRAM_CFG
#mem [CCSR 0x2110] = 0xC70C0000
mem [CCSR 0x2110] = 0xc7140008
#waitfor DRAM data initialization
wait500
下载Flash选择Connect SRAM或者在Debug/Run Configuration中修改为Connect模式,修改T2080RDB-PCIe_init_core.tcl,
/* line80 */
// mem [CCSR_ADDR 0x000C24] = 0xE8000000
mem [CCSR_ADDR 0x000C24] = 0xE0000000
/* line82 */
// mem [CCSR_ADDR 0x000C28] = 0x81F0001A
mem [CCSR_ADDR 0x000C28] = 0x81F0001B
/* line283 */
// mem [CCSR_ADDR [expr 0x124010 + $NOR_CS * 0x0C]] = 0xE8000101
mem [CCSR_ADDR [expr 0x124010 + $NOR_CS * 0x0C]] = 0xE0000101
/* line285 */
// mem [CCSR_ADDR [expr 0x1240A0 + $NOR_CS * 0x0C]] = 0xF8000000
mem [CCSR_ADDR [expr 0x1240A0 + $NOR_CS * 0x0C]] = 0xF0000000
/* line403 */
// # 0xE8000000 0xEFFFFFFF TLB1_4 NOR 128M
# 0xE0000000 0xEFFFFFFF TLB1_4 NOR 256M
修改T2080RDB-PCIe.mem,
/* line10 */
// 0xE8000000 0xEFFFFFFF NOR 128M
// 0xE0000000 0xEFFFFFFF NOR 256M
/* line27 */
// translate v:0x00000000E8000000 i:0x00E8000000 0x08000000
translate v:0x00000000E0000000 i:0x00E0000000 0x10000000
/* line41 */
reserved v:0x00000000E0000000 v:0x00000000E7FFFFFF
reserved p:0x00E0000000 p:0x00E7FFFFFF
reserved i:0x00E0000000 i:0x00E7FFFFFF
// reserved v:0x00000000E0000000 v:0x00000000E7FFFFFF
// reserved p:0x00E0000000 p:0x00E7FFFFFF
// reserved i:0x00E0000000 i:0x00E7FFFFFF
修改T2080RDB-PCIe_init.c,
/* line75 */
//# 0xE8000000 0xEFFFFFFF TLB1_4 NOR 128M
//# 0xE0000000 0xEFFFFFFF TLB1_4 NOR 256M
/* line237 */
// CCSR_SET_W(0xC24, 0xE8000000);
// CCSR_SET_W(0xC28, 0x81F0001A);
CCSR_SET_W(0xC24, 0xE0000000);
CCSR_SET_W(0xC28, 0x81F0001B);
/* line461 */
// CCSR_SET_W(0x010, 0xE8000101);
CCSR_SET_W(0x010, 0xE0000101);
/* line463 */
// CCSR_SET_W(0x0A0, 0xF0000000);
CCSR_SET_W(0x0A0, 0xF8000000);
修改T2080RDB-PCIe_init_sram.tcl,
/* line66 */
// mem [CCSR_ADDR 0x000C24] = 0xE8000000
mem [CCSR_ADDR 0x000C24] = 0xE8000000
/* line68 */
// mem [CCSR_ADDR 0x000C28] = 0x81f0001a
mem [CCSR_ADDR 0x000C28] = 0x81f0001b
/* line124 */
// mem [CCSR_ADDR [expr 0x124010 + $NOR_CS * 0x0C]] = 0xE8000101
mem [CCSR_ADDR [expr 0x124010 + $NOR_CS * 0x0C]] = 0xE0000101
/* line126 */
// mem [CCSR_ADDR [expr 0x1240A0 + $NOR_CS * 0x0C]] = 0xF8000000
mem [CCSR_ADDR [expr 0x1240A0 + $NOR_CS * 0x0C]] = 0xF0000000
/* line245 */
// # 0xE8000000 0xEFFFFFFF TLB1_4 NOR 128M
# 0xE0000000 0xEFFFFFFF TLB1_4 NOR 256M