数据输出寄存器可以读写,数据输入寄存器只能写。
引脚可以被配置为备选功能,一旦被选为了备选功能,读输入寄存器,仍体现了引脚上的输入,但向输出寄存器写入,并不会直接反应待引脚上,知道该引脚再次被配置为GPIO。 外部中断/DMA请求:
SIUL最大支持32个中断请求,根据MCU的不同分配资源不同(见信号描述)。
SIUL支持4和中断向量,每个向量包含8个引脚的中断。分在一组内的外部中断有着相同的优先级。每组的优先级是固定的,但是把那个引脚分在那个组内可以是通过配置改变的。
外部中断的初始化:
- Mask interrupts by clearing the EIREn bits in DIRER0
- Select the pin polarity by setting the appropriate IREEn bits in IREER0 and the appropriate IFEEn bits in IFEER0 as desired
- Configure the appropriate bits in the MSCR[0:511] register for the external interrupt
pin(s) desired as follows:
- Clear the OBE and ODE bits to disable output
- Set the IBE bit to enable the pin’s input buffer
- If using the internal pullup/pulldown, configure the appropriate PUE and PUS
fields
- Select the request desired between DMA or Interrupt by writing the appropriate
DIRSn bits in DIRSR0
- Select the desired glitch filter setup for the pins by writing the following:
- Write the Filter Counter setting to the desired value by writing the MAXCNT[3:0] bits in the IFMCn register for the respective external interrupt that is being used
- Set the Filter Clock Prescaler setting from 0 to 15 to the desired value by writing
the IFCP[3:0] bits in the IFCPR register
- Enable the glitch filter for the desired external interrupt pins by setting the
appropriate IFEn bits in IFER0
- Write to EIFn bits in DISR0 to as desired to clear any flags
- Enable the interrupt pins by setting the appropriate EIREn bits in DIRER0 外部中断管理;
用户可以通过SIUL2_DIRER0寄存器来使能或关闭中断,可以选择上升沿、下降沿或两者同时触发。SIUL2_IREER和SIUL2_IFEER两个寄存器控制IRQ边沿是否激活。