TX2440开发板Uboot移植教程

2019-07-12 23:23发布

 转载:http://blog.csdn.net/johnmcu/article/details/6561311
开发板:TX2440 UBOOT:u-boot-1.1.6.tar.bz2 GCC:arm-linux-gcc-3.3.2.tar.bz2 (注:不支持从NAND FLASH启动  1.解压U-BOOT-1.1.6,进入U-BOOT目录,修改Makefile smdk2410_config :       unconfig
        @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
加上 TX2440_config :    unconfig
        @$(MKCONFIG) $(@:_config=) arm arm920t TX2440 NULL s3c24x0
各项的意思如下:
arm: CPU
架构(ARCH)
arm920t: CPU
的类型(CPU),其对应于cpu/arm920t子目录。
TX2440: 
开发板的型号(BOARD),对应于board/TX2440目录。
NULL: 
开发者/或经销商(vender)
s3c24x0: 
片上系统(SOC)
  在第128行: ifeq ($(ARCH),arm) CROSS_COMPILE = arm-linux- 指定交叉编译器,我使用的是3.4.1,这里也可以写绝对路径   2.修改完Makefile后,在board目录下,新建自己的开发板目录TX2440,把smdk2410目录下的所有文件拷到TX2440,把smdk2410.c改为TX2440.c。修改该目录下的Makefile,把smdk2410.o改为TX2410.o COBJS  := TX2440.o flash.o   board目录下所有文件夹全部删除,只留TX2440   include/configs目录下创建板子的配置头文件,把smdk2410.h改名为TX2440.h,再把所有的文件全部删除,只留TX2440.h   测试能否编译成功: 执行make TX2440_config     //对应骤1 出现make: execvp: …………/mkconfig: 权限不够 查看mkconfig的权限,发现没有可执行权限,用chmod 764 mkconfig加上权限 然后再make,成功后可出现 Configuring for TX2440 board.....   修改SDRAM配置,在board/TX2440/lowlevel_init.S中,检查 #define B6_BWSCON     (DW32) 位宽为32 B1_BWSCON 改为(DW16  B5_BWSCON 改为(DW8   根据HCLK设置SDRAM 的刷新参数,主要是REFCNT寄存器,开发板HCLK100M 将  #define REFCNT   0x1113  改为  #define REFCNT  0x4f4   增加对S3C2440的支持2440的时钟计算公式、NAND操作和2410不太一样。 对于2440开发板,将FCLK设为400MHz,分频比为FCLKHCLKPCLK=148   修改board/TX2440/TX2440.c中的board_init函数 /* S3C2440: Mpll,Upll = (2*m * Fin) / (p * 2^s)  * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2  */ #define S3C2440_MPLL_400MHZ     ((0x7f<<12)|(0x02<<4)|(0x01)) #define S3C2440_UPLL_48MHZ      ((0x38<<12)|(0x02<<4)|(0x02)) #define S3C2440_CLKDIV          0x05    /* FCLK:HCLK:PCLK = 1:4:8 */   /* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s)  * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2  */ #define S3C2410_MPLL_200MHZ     ((0x5c<<12)|(0x04<<4)|(0x00)) #define S3C2410_UPLL_48MHZ      ((0x28<<12)|(0x01<<4)|(0x02)) #define S3C2410_CLKDIV          0x03    /* FCLK:HCLK:PCLK = 1:2:4 */   int board_init (void) {     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();     S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();       /* set up the I/O ports */     gpio->GPACON = 0x007FFFFF;     gpio->GPBCON = 0x00044555;     gpio->GPBUP = 0x000007FF;     gpio->GPCCON = 0xAAAAAAAA;     gpio->GPCUP = 0x0000FFFF;     gpio->GPDCON = 0xAAAAAAAA;     gpio->GPDUP = 0x0000FFFF;     gpio->GPECON = 0xAAAAAAAA;     gpio->GPEUP = 0x0000FFFF;     gpio->GPFCON = 0x000055AA;     gpio->GPFUP = 0x000000FF;     gpio->GPGCON = 0xFF95FFBA;     gpio->GPGUP = 0x0000FFFF;     gpio->GPHCON = 0x002AFAAA;     gpio->GPHUP = 0x000007FF;         /*support both of S3C2410 and S3C2440*/     if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))     {        /*FCLK:HCLK:PCLK = 1:2:4*/        clk_power->CLKDIVN = S3C2410_CLKDIV;               /* change to asynchronous bus mod */         __asm__(    "mrc    p15, 0, r1, c1, c0, 0 "    /* read ctrl register 是“ ”不是“/n ”*/                      "orr    r1, r1, #0xc0000000 "      /* Asynchronous        */                      "mcr    p15, 0, r1, c1, c0, 0 "    /* write ctrl register */                      :::"r1"                     );                           /* to reduce PLL lock time, adjust the LOCKTIME register */         clk_power->LOCKTIME = 0xFFFFFF;           /* configure MPLL */         clk_power->MPLLCON = S3C2410_MPLL_200MHZ;           /* some delay between MPLL and UPLL */         delay (4000);           /* configure UPLL */         clk_power->UPLLCON = S3C2410_UPLL_48MHZ;           /* some delay between MPLL and UPLL */         delay (8000);                  /* arch number of SMDK2410-Board */         gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;     }     else     {        /* FCLK:HCLK:PCLK = 1:4:8 */         clk_power->CLKDIVN = S3C2440_CLKDIV;           /* change to asynchronous bus mod */         __asm__(    "mrc    p15, 0, r1, c1, c0, 0 "    /* read ctrl register  */                      "orr    r1, r1, #0xc0000000 "      /* Asynchronous        */                      "mcr    p15, 0, r1, c1, c0, 0 "    /* write ctrl register */                      :::"r1"                     );           /* to reduce PLL lock time, adjust the LOCKTIME register */         clk_power->LOCKTIME = 0xFFFFFF;           /* configure MPLL */         clk_power->MPLLCON = S3C2440_MPLL_400MHZ;           /* some delay between MPLL and UPLL */         delay (4000);           /* configure UPLL */         clk_power->UPLLCON = S3C2440_UPLL_48MHZ;           /* some delay between MPLL and UPLL */         delay (8000);                 /* arch number of SMDK2440-Board */         gd->bd->bi_arch_number = MACH_TYPE_S3C2440;     }       /* adress of boot parameters */     gd->bd->bi_boot_params = 0x30000100;       icache_enable();     dcache_enable();       return 0; }   cpu/arm920t/s3c24X0/speed.c中修改: 在程序开头增加一行DECLARE_GLOBAL_DATA_PTR;,这样才可以使用gd变量 修改get_PLLCLK函数: static ulong get_PLLCLK(int pllreg) {     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();     ulong r, m, p, s;       if (pllreg == MPLL)     r = clk_power->MPLLCON;     else if (pllreg == UPLL)     r = clk_power->UPLLCON;     else     hang();       m = ((r & 0xFF000) >> 12) + 8;     p = ((r & 0x003F0) >> 4) + 2;     s = r & 0x3;       /* support both of S3C2410 and S3C2440 */     if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)        return((CONFIG_SYS_CLK_FREQ * m) / (p << s));     else         return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s));   /* S3C2440 */ }   修改get_HCLK, get_PCLK: /* for s3c2440 */ #define S3C2440_CLKDIVN_PDIVN        (1<<0) #define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1) #define S3C2440_CLKDIVN_HDIVN_1      (0<<1) #define S3C2440_CLKDIVN_HDIVN_2      (1<<1) #define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1) #define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1) #define S3C2440_CLKDIVN_UCLK         (1<<3)   #define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0) #define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4) #define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8) #define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9) #define S3C2440_CAMDIVN_DVSEN        (1<<12)   /* return HCLK frequency */ ulong get_HCLK(void) {     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();     unsigned long clkdiv;     unsigned long camdiv;     int hdiv = 1;       /* support both of S3C2410 and S3C2440 */     if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)     return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());     else     {         clkdiv = clk_power->CLKDIVN;         camdiv = clk_power->CAMDIVN;           /* work out clock scalings */           switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {         case S3C2440_CLKDIVN_HDIVN_1:             hdiv = 1;             break;           case S3C2440_CLKDIVN_HDIVN_2:             hdiv = 2;             break;           case S3C2440_CLKDIVN_HDIVN_4_8:             hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;             break;           case S3C2440_CLKDIVN_HDIVN_3_6:             hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;             break;         }           return get_FCLK() / hdiv;     } }   /* return PCLK frequency */ ulong get_PCLK(void) {     S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();     unsigned long clkdiv;     unsigned long camdiv;     int hdiv = 1;       /* support both of S3C2410 and S3C2440 */     if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)     return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());     else     {           clkdiv = clk_power->CLKDIVN;         camdiv = clk_power->CAMDIVN;           /* work out clock scalings */           switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {         case S3C2440_CLKDIVN_HDIVN_1:             hdiv = 1;             break;           case S3C2440_CLKDIVN_HDIVN_2:             hdiv = 2;             break;           case S3C2440_CLKDIVN_HDIVN_4_8:             hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;             break;           case S3C2440_CLKDIVN_HDIVN_3_6:             hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;             break;         }           return get_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);     }        }
在include/s3c24x0.h中定义, 在129行S3C24X0_CLOCK_POWER结构体中 增加:S3C24X0_REG32    CAMDIVN;    /* for s3c2440*/  typedef struct {
S3C24X0_REG32 LOCKTIME;
S3C24X0_REG32 MPLLCON;
S3C24X0_REG32 UPLLCON;
S3C24X0_REG32 CLKCON;
S3C24X0_REG32 CLKSLOW;
S3C24X0_REG32 CLKDIVN;
S3C24X0_REG32   CAMDIVN;  /* for s3c2440*/
} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;


此时,基本配置完成: 重新执行 make TX2440_config     make all  生成u-boot.bin 由于还没有增加NAND Flash的支持,所以可烧入NOR Flash中运行。
 要在nand flash中运行,需要增加nand flash驱动。 支持NAND Flash 首先在配置文件include/configs/TX2440.h的宏CONFIG_COMMANDS中增加CFG_CMD_NAND (大概在82) 编译,出现nand.c的错误和警告 解决:在include/configs/TX2440.h的最后面增加3个宏: /*NAND flash settings*/ #define CFG_NAND_BASE        0      //无实际意义:基地址,在board_nand_init中重新定义 #define CFG_MAX_NAND_DEVICE     1   //NAND Flash设备数目为1 #define NAND_MAX_CHIPS          1   //每个NAND设备由1NADN芯片组成 修改配置文件后再编译,只有一个错误了“board_nand_init”函数未定义   board_nand_init需要自己编写,在cpu/arm920t/s3c24x0下新建nand_flash.c 编写之前,需要针对S3C2440 NAND Flash定义一些数据结构和函数 include/s3c24x0.h中增加S3C2440_NAND数据结构(168行) /* NAND FLASH (see S3C2440 manual chapter 6) */ typedef struct {     S3C24X0_REG32 NFCONF;     S3C24X0_REG32 NFCONT;     S3C24X0_REG32 NFCMD;     S3C24X0_REG32 NFADDR;     S3C24X0_REG32 NFDATA;     S3C24X0_REG32 NFMECCD0;     S3C24X0_REG32 NFMECCD1;     S3C24X0_REG32 NFSECCD;     S3C24X0_REG32 NFSTAT;     S3C24X0_REG32 NFESTAT0;     S3C24X0_REG32 NFESTAT1;     S3C24X0_REG32 NFMECC0;     S3C24X0_REG32 NFMECC1;     S3C24X0_REG32 NFSECC;     S3C24X0_REG32 NFSBLK;     S3C24X0_REG32 NFEBLK; } /*__attribute__((__packed__))*/ S3C2440_NAND;   include/s3c2410.h中仿照S3C2410_GetBase_NAND函数(96行) 定义2440的函数: static inline S3C2440_NAND * const S3C2440_GetBase_NAND(void) {     return (S3C2440_NAND * const)S3C2410_NAND_BASE; }   cpu/arm920t/s3c24x0/nand_flash.c中添加代码,是从Linux-2.6.13/drivers/mtd/nand/s3c2410.c中移植过来的,代码略。   修改cpu/arm920t/s3c24x0/Makefile COBJS  =  加上一项nand_flash.o   编译后生成uboot镜像,但这里注意,现在还不支持NAND FLASH启动,只能烧到NOR FLASH中。要支持NAND FLASH启动,要修改cpu/arm920t/start.S,还要编写nand启动函数,这里先不考虑,复制现成的代码过来,以后再说。   支持网卡芯片DM9000 driver下,有网卡驱动DM9000x.c  DM9000x.h DM9000接在BANK4,位宽16   include/configs/TX2440.h中设置网卡基地址: 56行处,将CS8900的定义改成: #define CONFIG_DRIVER_DM9000       1 #define CONFIG_DM9000_BASE      0x20000300 #define DM9000_IO            CONFIG_DM9000_BASE #define DM9000_DATA         (CONFIG_DM9000_BASE + 4) #define CONFIG_DM9000_USE_16BIT   drivers目录下,只留nand nand_legacy dm9000x.c dm9000x.h Makefile 其他文件全部删除,修改Makefile: COBJS = dm9000x.o 修改顶层目录的Makefile:209行的内容 LIBS += drivers/sk98lin/libsk98lin.a   删除 可以将顶层目录下没用的lib_x 文件夹删除,只留lib_arm  lib_generic 编译可生成支持网卡的uboot   设置Linux启动参数 77行处,加两个宏定义: /* for tag(s) to transfer message to kernel*/ #define CONFIG_SETUP_MEMORY_TAGS    1 #define CONFIG_CMDLINE_TAG          1 #include 后面的一些启动参数修改如下:   /*自启动前延时3*/ #define CONFIG_BOOTDELAY     3 /*默认的命令行参数*/ #define CONFIG_BOOTARGS    "noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0" /*默认的网络设置*/ #define CONFIG_ETHADDR   08:00:3e:26:0a:5b #define CONFIG_NETMASK          255.255.255.0 #define CONFIG_IPADDR       192.168.220.6 #define CONFIG_SERVERIP     192.168.220.19 /*#define CONFIG_BOOTFILE   "elinos-lart" */ /*自动启动命令*/ #define CONFIG_BOOTCOMMAND  "nboot 0x32000000 0 0x50000; bootm 0x32000000"   这个是uboot的命令提示符,可修改 #define    CFG_PROMPT    "TX2440>"  /* Monitor Command Prompt   */