DSP

学习DSP外设之UART的配置和应用

2019-07-13 09:41发布

站内文章 / DSP
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一、Initialization

The following steps are required to initialize the UART: 0.给UART模块上电 1.Perform the necessary device pin multiplexing setup (see your device-specific data manual). 2.Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers(DLL and DLH). Divisor = UART input clock frequency／（Desired baud rate * 16）     当 MDR.OSM _ SEL = 0  Divisor = UART input clock frequency／（Desired baud rate * 13）     当 MDR.OSM _ SEL = 1  3.If the FIFOs will be used（FIFOEN =1 in FCR）,The FIFOEN bit in FCR must be set first, before the other bits in FCR are configured. Select the desired trigger level and enable the FIFOs by writing the appropriate values to the FIFO control register (FCR).  Clear the transmitter FIFO and Receiver FIFO by set TXCLR=1 and RXCLR =1. 4.Choose the desired protocol settings by writing the appropriate values to the line control register(LCR).  e.g. set PEN =0(No PARITY),STB=0(1stop bit),WLS=0x3(8bits) 5.set IER controller if you need interrupt. 6.If autoflow control is desired, write appropriate values to the modem control register (MCR). Note thatall UARTs do not support autoflow control, see your device-specific data manual for supported features. 7.Choose the desired response to emulation suspend events by configuring the FREE bit and enable the UART by setting the UTRST and URRST bits in the power and emulation management register(PWREMU_MGMT).  Here I set  UTRST =1(Transmitter is enabled. ) , URRST =1(Receiver is enabled. ) ,FREE=1(Free-running mode is enabled; UART continues to run normally )
8.根据需求配置中断 IER寄存器（一般配置为IER=0x5，即接收中断和receiver line status异常中断） 9.映射中断函数到中断向量表  

二、transmit

手册中写道 The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is afunction of the UART line control register (LCR). Based on the settings chosen in LCR, the UARTtransmitter sends the following to the receiving device: 1 START bit 5,6,7,or8databits 1 PARITY bit (optional) 1, 1.5, or 2 STOP bits THR receives data from the internal data bus, and when TSR is ready, the UART moves the data fromTHR to TSR. The UART serializes the data in TSR and transmits the data on the UARTn_TXD pin. In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled in the interruptenable register (IER), an interrupt is generated. This interrupt is cleared when a character is loaded intoTHR or the interrupt identification register (IIR) is read. In the FIFO mode, the interrupt is generated whenthe transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or IIR is read.
串口发送时，只需要判断THR（即FIFO）为空，想THR写入即可 流程 1.读取TEMT in LSR来判断THR和TSR是否为空， 循环等待直到THRE =1  2.可以加一点延迟，为了稳定我这里加了30us延迟，如果不加延迟也能稳定运行可以不加 3.循环发送数据 a.写入数据到THR b.等待UART发送数据，发送完成后THRE=1 c.重复执行a，b，直到数据发送完成

三、receive

手册中写道： The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16×receiverclock. Receiver section control is a function of the UART line control register (LCR). Based on the settingschosen in LCR, the UART receiver accepts the following from the transmitting device:
1 START bit 5,6,7,or8databits 1 PARITY bit (optional) 1 STOP bit (any other STOP bits transferred with the above data are not detected)
RSR receives the data bits from the UARTn_RXD pin. Then RSR concatenates the data bits and movesthe resulting value into RBR (or the receiver FIFO). The UART also stores three bits of error statusinformation next to each received character, to record a parity error, framing error, or break. In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabledin the interrupt enable register (IER), an interrupt is generated. This interrupt is cleared when the characteris read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger levelselected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below thetrigger level.  接收时，判断RBR中有未读数据，读出该数据，再判断是否有新数据，有则继续读出来。但是一次中断读取次数不能超过配置的FIFO大小，超出则溢出了。当达到FIFO大小时，例如有8字节，读出8字节后则停止，等待下一次UART中断，再读数据。 流程 1.读取IIR状态，判断是否属于receiver相关中断（INTID = 2 | INTID = 3 | INTID = 6 ） 2.读取DR in LSR来判断Data是否ready， 循环等待直到DR =1  3.循环读取数据 a.等待DR=1 in LSR register b.从RBR中读出数据到内存 c.判断读取字节数是否超出FIFO长度，超出则结束读取，等待下一个接收中断 d.重复执行a，b，直到数据发送完成




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