原文地址：DSP28_SysCtrl.h头文件寄存器说明（一）作者：simplorer //
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:    DSP28_SysCtrl.h
//
// TITLE:    DSP28 Device System Control Register Definitions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 27 May 2002 | L.H. | No change
//########################################################################### #ifndef DSP28_SYS_CTRL_H
#define DSP28_SYS_CTRL_H //---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//
// High speed peripheral clock register bit definitions:
struct HISPCP_BITS  {   // bits  description
   Uint16 HSPCLK:3;       // 2:0   Rate relative to SYSCLKOUT
   Uint16 rsvd1:13;       // 15:3  reserved
}; union HISPCP_REG {
   Uint16                all;
   struct HISPCP_BITS  bit;
}; // Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS  {   // bits  description
   Uint16 LSPCLK:3;       // 2:0   Rate relative to SYSCLKOUT
   Uint16 rsvd1:13;       // 15:3  reserved
}; union LOSPCP_REG {
   Uint16                all;
   struct LOSPCP_BITS  bit;
}; // Peripheral clock control register bit definitions:
struct PCLKCR_BITS  {   // bits  description
   Uint16 EVAENCLK:1;     // 0     Enable high speed clk to EV-A
   Uint16 EVBENCLK:1;     // 1     Enable high speed clk to EV-B
   Uint16 rsvd1:1;        // 2
   Uint16 ADCENCLK:1;     // 3     Enable high speed clk to ADC
   Uint16 rsvd2:4;        // 7:4   reserved
   Uint16 SPIENCLK:1;     // 8     Enable low speed clk to SPI
   Uint16 rsvd3:1;        // 9     reserved
   Uint16 SCIENCLKA:1;    // 10    Enable low speed clk to SCI-A
   Uint16 SCIENCLKB:1;    // 11    Enable low speed clk to SCI-B
   Uint16 MCBSPENCLK:1;   // 12    Enable low speed clk to McBSP
   Uint16 rsvd4:1;        // 13    reserved
   Uint16 ECANENCLK:1;    // 14    Enable system clk to eCAN
}; union PCLKCR_REG {
   Uint16                all;
   struct PCLKCR_BITS  bit;
};   // System control and status register bit definitions:
struct SCSR_BITS {      // bits  description
   Uint16 WDOVERRIDE:1;   // 0     Allow watchdog disable
   Uint16 WDENINT:1;      // 1     Enable/disable WD interrupt
   Uint16 rsvd1:14;       // 15:2  reserved
}; union SCSR_REG {
   Uint16              all;
   struct SCSR_BITS  bit;
}; //---------------------------------------------------------------------------
// System Control Register File:
//
struct SYS_CTRL_REGS {
   Uint16  rsvd1[10];            // 0-9
   union HISPCP_REG HISPCP;      // 10: High-speed peripheral clock pre-scaler
   union LOSPCP_REG LOSPCP;      // 11: Low-speed peripheral clock pre-scaler
   union PCLKCR_REG PCLKCR;      // 12: Peripheral clock control register
   Uint16  rsvd2;                // 13
   Uint16  LPMCR0;               // 14: Low-power mode control register 0
   Uint16  LPMCR1;               // 15: Low-power mode control register 1
   Uint16  rsvd3;                // 16
   Uint16  PLLCR;                // 17: PLL control register
   union SCSR_REG SCSR;          // 18: System control and status register
   Uint16  WDCNTR;               // 19: WD counter register
   Uint16  rsvd4;                // 20
   Uint16  WDKEY;                // 21: WD reset key register
   Uint16  rsvd5[3];             // 22-24
   Uint16  WDCR;                 // 25: WD timer control register
   Uint16  rsvd6[6];             // 26-31
};

 
struct  CSMSCR_BITS {      // bit   description
   Uint16     SECURE:1;    // 0     Secure flag
   Uint16     rsvd1:14;    // 14-1  reserved
   Uint16     FORCESEC:1;  // 15    Force Secure control bit };
union CSMSCR_REG {
   Uint16       all;
   struct CSMSCR_BITS bit;
};
struct  CSM_REGS {     
   Uint16         KEY0;       // KEY reg bits 15-0
   Uint16         KEY1;       // KEY reg bits 31-16
   Uint16         KEY2;       // KEY reg bits 47-32
   Uint16         KEY3;       // KEY reg bits 63-48
   Uint16         KEY4;       // KEY reg bits 79-64
   Uint16         KEY5;       // KEY reg bits 95-80
   Uint16         KEY6;       // KEY reg bits 111-96
   Uint16         KEY7;       // KEY reg bits 127-112
   Uint16         rsvd1;      // reserved
   Uint16         rsvd2;      // reserved
   Uint16         rsvd3;      // reserved
   Uint16         rsvd4;      // reserved
   Uint16         rsvd5;      // reserved
   Uint16         rsvd6;      // reserved
   Uint16         rsvd7;      // reserved
   union CSMSCR_REG CSMSCR;