DSP

嵌入式 视频处理前端

2019-07-13 11:31发布

站内文章 / DSP
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原文链接：http://blog.csdn.net/skdkjzz/article/details/17073077
VPFE 1.OVERVIEW 1.1 CCDC 1）产生SD，HD时序信号 2）可编程镜头阴影校正（ Lens Shading Correction）. 3）支持BT656，YCBCR422（8BIT，16BIT，WITH HS，VS），及14BIT RAW DATA FROMCCD/CMOS 4) 可编程14BIT 到8BIT输出 5）可通过外部写能动信号EN控制向DDR写数据 6）SENSOR CLK可达75MHZ，若用到H3A，则只能达67.5MHZ 7）DEFECT CORRECT 1.2.H3A 1）auto white balance and auto eexposure by collectingmetrics（统计） 2）读写DDR 3）只接收RAW DATA 1.3.IPIPE 1）只接收RAW DATA ，且转换14BIT RAW DATA为YCBCR422或YCRCR422 RESIZE 2）支持RGB Bayer pattern，经过彩 {MOD}空间转换也支持CMYG 3）每个分量增益控制 4）可编程的RGB TO YCBCR的转换系数 5）可配置成仅RESIZE模式，即直接YCBCR422 RESIZE，不经过其它模块处理 6）RGB (32bit/16bit) output to SDRAM 7）要求至少BLANK 8PIXEL/行，4行 BLANK，在ONE SHOT 下，至少10行 BLANK，在处理之后 8）最大支持1344PIXEL 输入输出宽度    9）DEFECT CORRECT 1.4.IPIPEIF 1）读CCDC，SDRAM，写IPIPE 2）重新调整 HD, VD, and PCLK timing to the IPIPE input. 3）dark-frame subtract黑 {MOD}帧消除法降噪（用于长时间瀑光引起的噪声点） 2.引脚IO 接口 1. YIN[7..0]/CCDIN[7..0] 2. CIN[5..0]/CCDIN[13..0] 3.PCLK 4.CAM_HD,CAM_VD 5.CAM_WEN_FIELD:/设 CCD Write Enable/Field ID signal      1）作FIELD标识信号，FLDMODE定类型提供，由CCD/CMOSFIDMD/FLDPOL      2）作WEN用，EXWEN打开，WENLOG设定AND 或 OR，与在SPH, NPH, SLV,NLV内的有效像素相AND或OR   RAM模式引脚: 以上全需用到 另少于14BIT时,一般用CCD[13..0]高位,舍去底位,当用时SPI时除外 ----------------------------------------------------------------   引脚配置REG: PINMUX0(VPFE.PDFPAGE38) 3。VPFE/ISPIntegration VPSS Events:9个作为中断送ARM，4个作为EVENT送EDMA Number   AcronymModule     Description
0     CCDC VDINT0 CCDC   Triggeredafter a programmable number of input lines for each frame.
1 CCDC VDINT1 CCDC Triggered after a programmable number of inputlines for each frame.
2 CCDC VDINT2 CCDC Triggered at the rising edge of WEN signal
3 H3AINT H3A Triggered at the end of AF or AEW writes to DDR foreach frame
4 VENCINT VENC Triggered at the rising edge of VSYNC
5 OSDINT OSD Triggered at the end of each frame read from DDR
6 IPIPEIFINT IPIPEIF Triggered at the rising edge of VD ifenabled
7 IPIPE_INT0_HST IPIPE Triggered when Histogram processing isfinished for each frame
8 IPIPE_INT1_SDR IPIPE Triggered when writes to DDR are finishedfor each frame
9 IPIPE_INT2_RZA IPIPE Triggered when the number of linesprogrammed has been output of RZA
10 IPIPE_INT3_RZB IPIPE Triggered when the number of linesprogrammed has been output of RZB
12 IPIPE_INT5_MMR IPIPE Triggered when MMR modifications for thenext frame can be made   中断：VPSSBL.INTSEL选择 INT Number Acronym
0 VPSSINT0
1 VPSSINT1
2 VPSSINT2
3 VPSSINT3
4 VPSSINT4
5 VPSSINT5
6 VPSSINT6
7 VPSSINT7
8 VPSSINT8 事件：VPSSBL.EVTSEL选择 Event Number Binary Event Name
4 0000100 VPSSEVT1
5 0000101 VPSSEVT2
6 0000110 VPSSEVT3
7 0000111 VPSSEVT4   VPSS REG： VPFE Module Register Map
VPSSRegisters                  Address Range                   Size
VPSSCLK                        0x01C700000x01C7007F            128B
H3A                            0x01C700800x01C700FF            128B
IPIPEIF                        0x01C701000x01C701FF            256B
OSD                            0x01C70200 0x01C702FF            256B
VENC                           0x01C704000x01C705FF            512B
CCDC                        

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