本人根据对DSP的理解翻译部分重要的术语，不能保证术语本身翻译的准确性，但是可以保证对术语解释部分翻译的意思基本正确。 如有疑问请回复。转载请注明CSDN。   英文原版来自于TMS320C64X+ DSP Cache User's Guide 1.3节。Cache Terms and Definitions Table 1-1 Cache Terms and Definitions Ti 定义了若干与片上结构有关的术语，对这些术语的理解是掌握片上结构的必要条件。 1:allocation :The process of finding a location in the cache to store newly cached data. This process can include
evicting data that is presently in the cache to make room for the new data. 将最新的需要缓存的数据在缓存中找到一个位置进行存储的过程（这个位置通常是指一个缓存行）。 这个过程也包括了将此位置的原有缓存（行）数据驱逐出去，从而给新数据让出空间的情况。   2:hit: A cache hit occurs when the data for a requested memory location is present in the cache. The
opposite of a hit is a miss. A cache hit minimizes stalling, since the data can be fetched from the cache
much faster than from the source memory. The determination of hit versus miss is made on each level
of the memory hierarchy separately-a miss in one level may hit in a lower level. 当所需要访问的数据正好在缓存中的对应location时时，我们称之为hit，相
反的一种情形则是缺失（miss），缓存命中会减低阻塞发生的几率，因为数据可
以直接从速度很快的缓存中取得，在一个存储器分级的系统中（例如C64+ DSP,存储器分L1,L2,DDR2,这个就是分级）， 缓存是否命中与该缓存所处的级别无关—即某一级别的缓存缺失的情况下，其下一级别的缓存
可能是命中的 3.miss: A cache miss occurs when the data for a requested memory location is not in the cache. A miss may
stall the requestor while the line frame is allocated and data is fetched from the next lower level of
memory. In some cases, such as a CPU write miss from L1D, it is not strictly necessary to stall the
CPU. Cache misses are often divided into three categories: compulsory misses, conflict misses, and
capacity misses. 缓存缺失（cache miss）发生在当所需要的数据不在缓存中对应location的时候，缺失会
阻塞访问请求，因为这个line frame 已经被锁定了，但是数据还得从下一级存
储器里面取得。某些情形下，比如CPU 对L1D 的写缺失，是不一定就能阻塞
CPU 的。缓存缺失有三种情况：必然缺失（compulsory misses，即自上电起第一次访问这个地址，是肯定从未cache过的），冲突缺失（conflict
misses，即所需要的location恰好被其他合法（invidate）的数据使用）和容量缺失（capacity misses，即缓存已经满了）。 4 validate :When a cache line holds data that has been fetched from the next level memory, that line frame is
valid. The invalid state occurs when the line frame holds no data, either because nothing has been
cached yet, or because previously cached data has been invalidated for whatever reason (coherence
protocol, program request, etc.). The valid state makes no implications as to whether the data has been
modified since it was fetched from the lower-level memory; rather, this is indicated by the dirty or clean
state of the line. 当一个缓存行已经取得了下一级存储器的数据，我们称此
缓存行的line-frame 是合法（validate）的，或者说有效的。非法（无效）的状态发生在这个line frame 没有任何数
据，或者是因为没有任何数据被缓存，或者因为先前被缓存进来的数据已经是
非法的了，比如缓存一致性策略，编程请求等等 5：invalidate :The process of marking valid cache lines as invalid in a particular cache. Alone, this action discards the
contents of the affected cache lines, and does not write back any updated data. When combined with a
writeback, this effectively updates the next lower level of memory that holds the data, while completely
removing the cached data from the given level of memory. Invalidates combined with writebacks are
referred to as writeback-invalidates, and are commonly used for retaining coherence between caches 使一个有效的缓存行（valid cache lines）变成无效
（invalid）的过程称之为使无效，孤立的讲，这个动作忽略了所影响的行的（其
他字节）内容，并且不会回写任何已经更新后的数据。此时若发起一个回写操
作， 则会使下一级存储器更新其内容。因此， 使无效（invalidates） 和回写
（writeback）合并在一起可以当做是回写使无效（writeback-invalidates）， 这
种行为通常是为了维持缓存一致性 6:Least Recently Used (LRU) allocation :For set-associative and fully-associative caches, least-recently used allocation refers to the method used to choose among line frames in a set when allocating space in the cache. When all of the line
frames in the set that the address maps to contain valid data, the line frame in the set that was read or
written the least recently (furthest back in time) is selected to hold the newly cached data. The selected
line frame is then evicted to make room for the new data. 对于若干排-相关
联（set-associative）和全关联型(fully-associative)的缓存，最近最少用来分配的空间意味着当有新数据被缓存进来
时在此排（set）的line frame 中被优先选择使用。即使所有的空间都被使用了，
那么使用最不频繁的空间用来存放最新被缓存进来的数据。此时被选择的line
frame 的数据将会被驱逐出去。  7:line :A cache line is the smallest block of data that the cache operates on. The cache line is typically much
larger than the size of data accesses from the CPU or the next higher level of memory. For instance,
although the CPU may request single bytes from memory, on a read miss the cache reads an entire
line's worth of data to satisfy the request. 一个缓存行是缓存控制器操作的最小的数据单位。缓存行通常
都远远大于CPU 或者更高级别的存储器所需要访问数据的大小。例如，CPU
可能会请求一个字节的数据，如果读缺失，缓存控制器会读取一整行缓存（缓
存行）来满足这次请求。 8 line frame : A location in a cache that holds cached data (one line), an associated tag address, and status
information for the line. The status information can include whether the line is valid, dirty, and the
current state of that line's LRU. 行信息集中会存放一行缓存的数据，以及与此对应
的tag 地址，此行的状态信息（status）。其中状态信息包括是否是有效的，肮
脏的，LRU 状态 9:Set-associative cache A set-associative cache contains multiple line frames that each lower-level memory location can be
held in. When allocating room for a new line of data, the selection is made based on the allocation
policy for the cache. The C64x+ devices employ a least recently used allocation policy for its
set-associative caches. 一个排-关联型(set-associative)的缓存包含几个line
frame，这样其较低一级的存储器的地址可以被缓存进来。当为新数据锁定一个
新空间的时候，究竟是选择哪个line frame 要有此缓存的锁定政策来决定。
C64x 设备使用了LRU 的方案。 10:read allocate A read-allocate cache only allocates space in the cache on a read miss. A write miss does not cause
an allocation to occur unless the cache is also a write-allocate cache. For caches that do not write
allocate, the write data would be passed on to the next lower-level cache. 具有读分配功能的缓存仅仅在读缺失的时候进行
空间分配。写缺失的时候不会进行分配， 除非这个缓存同时又具有写分配
（write-allocate）功能。如果不具备写分配的功能，数据将会被写到下一级缓
存中。 11  Write allocate A write-allocate cache allocates space in the cache when a write miss occurs. Space is allocated
according to the cache's allocation policy (LRU, for example), and the data for the line is read into the
cache from the next lower level of memory. Once the data is present in the cache, the write is
processed. For a writeback cache, only the current level of memory is updated-the write data is not
immediately passed to the next level of memory. 一个具有写分配缓存功能的存储器可以在写缺失
发生时分配空间，方法是根据缓存的分配策略（比如LRU），此时这一行的数
据会先从下一级存储器读取，然后CPU 再去更新此行的缓存数据。 12 Writeback The process of writing updated data from a valid but dirty cache line to a lower-level memory. After the
writeback occurs, the cache line is considered clean. Unless paired with an invalidate (as in
writeback-invalidate), the line remains valid after a writeback ：将一个合法并且更新过数据的缓存行的数据写到较低一
级存储器的过程称为回写，当回写发生后，缓存行的数据被认为已经清除了，
但是回写后此行还是标记为合法。除非再来一次使无效操作 13 Writeback cache A writeback cache will only modify its own data on a write hit. It will not immediately send the update to
the next lower-level of memory. The data will be written back at some future point, such as when the
cache line is evicted, or when the lower-level memory snoops the address from the higher-level
memory. It is also possible to directly initiate a writeback for a range of addresses using cache control
registers. A write hit to a writeback cache causes the corresponding line to be marked as dirty-that is,
the line contains updates that have yet to be sent to the lower levels of memory. 这种类型的缓存，当发生写命中时，将只
修改自己的数据，不会立即将此数据送到较低一级存储器。数据将会在未来某
个合适的时刻写到下一级存储器，比如，当此缓存行被驱逐，或者是较低一级
存储器向较高一级存储器发送地址探测信号。也有可能是直接通过缓存控制寄
存器对一个连续区域发送回写初始化信号。一个写命中意味着缓存中的这个
行被标记为dirty，也就是说，此行包含着已经更新的但是还没有被送到较低一
级存储器的数据。