uPP通信（2）---FPGA篇 2013-01-13 09:59:32 分类： 嵌入式   系统架构   本系统组成如下图，FPGA挨个读取24个AD通道中的数据，然后通过UPP方式传送给OMAPL138中的DSP核，经过一系列运算，DSP核通过DSPLINK方式将数据送到ARM核。     FPGA数据读取、存储、传送、数据识别问题   因为OMAPL138需要识别传送上来的数据是对应哪个通道的。所以FPGA对数据必须做一些处理以便于OMAPL138对数据分门别类。 方法一： 在FPGA中生成一个FIFO，挨个读取24个AD通道中的数据按次序存放到FIFO中，FIFO中存放满预定大小的数据量时再上传给OMAPL138，这样OMAPL138就知道第一个数据是对应通道1的，第二个数据是对应通道2的。 优点：简单，容易实现 缺点：如果其中一个数据出错或者漏传，那后面的一大堆数据都会被错误归类。 方法二： AD通道输出数据是16位，将其扩展为32位，高16位作为标志位。例如，如果第一个AD通道读出来的0xDE33,那扩展为32位时其数据为0x0001DE33。OMAPL138通过其高16位辨别这个数据是哪个通道的。 优点：不再像方法一担心数据传错了，传错也不会危害到整体。 缺点：OMAPL138的UPP通信时16位的数据线，原来是需要传送数据，现在还要传送标志数据，这样直接导致传输效率打5折。但是对于能够到达150MB/s吞吐量的UPP来说，就算传输只能达到50%，也是能满足我目前这个系统的。     读取AD： 以下是读取ad的代码，状态机的状态比较多，比较麻烦。
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1. module ads_ddio (
   
2.                         clk,
   
3.                         rst,
   
4.                         eoc,
   
5.                         datain,
   
6.                         dataout,
   
7.                         f_ncs,
   
8.                         f_nrd,
   
9.                         fifo_wr,
   
10.                         f_c1,
    
11.                         f_c2,
    
12.                         f_c3,
    
13.                         f_c4,
    
14.                         f_c5,
    
15.                         f_c6
    
16.                     );
    
17. 
    
18.                 
    
19. input             clk,rst;
    
20. input[1:0]        eoc;
    
21. input[15:0]     datain;
    
22. output             f_c1, f_c2, f_c3, f_c4, f_c5, f_c6;
    
23. output[1:0]      f_ncs;
    
24. output[1:0]             f_nrd;
    
25. output fifo_wr;
    
26. output[31:0]     dataout;
    
27. 
    
28. 
    
29. reg[7:0] counter;
    
30. reg[31:0] data_reg;
    
31. reg state;
    
32. reg[1:0] eoc1;
    
33. reg[5:0] cstate,nstate;
    
34. reg[1:0] f_nrd_reg,f_ncs_reg;
    
35. reg fifo_wr_reg;
    
36. 
    
37. parameter     SET_COUNT          = 8'hff, 
    
38. 
    
39.                 SET_CSRD_C1UA = 8'd23,
    
40.                 SET_DATA_C1UA = 8'd24,
    
41.                 SET_CSRD_C1UB = 8'd26,
    
42.                 SET_DATA_C1UB = 8'd27,
    
43.                 SET_CSRD_C1UC = 8'd29,
    
44.                 SET_DATA_C1UC = 8'd30,
    
45.                 SET_CSRD_C1IA = 8'd32,
    
46.                 SET_DATA_C1IA = 8'd33,
    
47.                 SET_CSRD_C1IB = 8'd35,
    
48.                 SET_DATA_C1IB = 8'd36,
    
49.                 SET_CSRD_C1IC = 8'd38,
    
50.                 SET_DATA_C1IC = 8'd39,    
    
51.                 
    
52.                 SET_CSRD_C2UA = 8'd41,
    
53.                 SET_DATA_C2UA = 8'd42,
    
54.                 SET_CSRD_C2UB = 8'd44,
    
55.                 SET_DATA_C2UB = 8'd45,            
    
56.                 SET_CSRD_C2UC = 8'd47,
    
57.                 SET_DATA_C2UC = 8'd48,    
    
58.                 SET_CSRD_C2IA = 8'd50,
    
59.                 SET_DATA_C2IA = 8'd51,            
    
60.                 SET_CSRD_C2IB = 8'd53,
    
61.                 SET_DATA_C2IB = 8'd54,
    
62.                 SET_CSRD_C2IC = 8'd56,
    
63.                 SET_DATA_C2IC = 8'd57,
    
64.                     
    
65.                 SET_FIFO_DATA = 8'd60, //上个状态+3
    
66.                 
    
67.                 SET_IDLE          = 8'd62;
    
68.                 
    
69.                 
    
70. parameter     IDLE                 = 6'd0,
    
71.                 CSRDN_C1UA        = 6'd1,
    
72.                 DATA_C1UA         = 6'd2,
    
73.                 DATA1_C1UA = 6'd3,
    
74.                 CSRDN_C1UB        = 6'd4,
    
75.                 DATA_C1UB         = 6'd5,
    
76.                 DATA1_C1UB = 6'd6,
    
77.                 CSRDN_C1UC        = 6'd7,
    
78.                 DATA_C1UC         = 6'd8,
    
79.                 DATA1_C1UC = 6'd9,
    
80.                 CSRDN_C1IA        = 6'd10,
    
81.                 DATA_C1IA         = 6'd11,
    
82.                 DATA1_C1IA = 6'd12,
    
83.                 CSRDN_C1IB        = 6'd13,
    
84.                 DATA_C1IB         = 6'd14,
    
85.                 DATA1_C1IB = 6'd15,
    
86.                 CSRDN_C1IC        = 6'd16,
    
87.                 DATA_C1IC         = 6'd17,
    
88.                 DATA1_C1IC = 6'd18,
    
89.                 
    
90.                 CSRDN_C2UA        = 6'd19,
    
91.                 DATA_C2UA         = 6'd20,
    
92.                 DATA1_C2UA = 6'd21,
    
93.                 CSRDN_C2UB        = 6'd22,
    
94.                 DATA_C2UB         = 6'd23,
    
95.                 DATA1_C2UB = 5'd24,
    
96.                 CSRDN_C2UC        = 6'd25,
    
97.                 DATA_C2UC         = 6'd26,
    
98.                 DATA1_C2UC = 6'd27,
    
99.                 CSRDN_C2IA        = 6'd28,
    
100.                 DATA_C2IA         = 6'd29,
     
101.                 DATA1_C2IA = 6'd30,
     
102.                 CSRDN_C2IB        = 6'd31,
     
103.                 DATA_C2IB         = 6'd32,
     
104.                 DATA1_C2IB = 6'd33,
     
105.                 CSRDN_C2IC        = 6'd34,
     
106.                 DATA_C2IC         = 6'd35,
     
107.                 DATA1_C2IC = 6'd36,
     
108.                 FIFO_DATA = 6'd37;                
     
109. 
     
110. 
     
111. wire csrd_n_c1ua_req;
     
112. wire csrd_n_c1ub_req;
     
113. wire csrd_n_c1uc_req;
     
114. wire csrd_n_c1ia_req;
     
115. wire csrd_n_c1ib_req;
     
116. wire csrd_n_c1ic_req;
     
117. 
     
118. wire csrd_n_c2ua_req;
     
119. wire csrd_n_c2ub_req;
     
120. wire csrd_n_c2uc_req;
     
121. wire csrd_n_c2ia_req;
     
122. wire csrd_n_c2ib_req;
     
123. wire csrd_n_c2ic_req;
     
124. 
     
125. 
     
126. wire data_c1ua_req;
     
127. wire data_c1ub_req;
     
128. wire data_c1uc_req;
     
129. wire data_c1ia_req;
     
130. wire data_c1ib_req;
     
131. wire data_c1ic_req;
     
132. 
     
133. wire data_c2ua_req;
     
134. wire data_c2ub_req;
     
135. wire data_c2uc_req;
     
136. wire data_c2ia_req;
     
137. wire data_c2ib_req;
     
138. wire data_c2ic_req;
     
139. 
     
140. wire fifo_data_req;
     
141. 
     
142. wire idle_req;
     
143. 
     
144. assign f_c1 = 1'b1;
     
145. assign f_c2 = 1'b0;
     
146. assign f_c3 = 1'b1; 
     
147. assign f_c4 = 1'b0;
     
148. assign f_c5 = 1'b0;
     
149. assign f_c6 = 1'b0;
     
150. 
     
151. assign dataout = data_reg;
     
152. 
     
153. assign csrd_n_c1ua_req = (counter == SET_CSRD_C1UA);
     
154. assign csrd_n_c1ub_req = (counter == SET_CSRD_C1UB);
     
155. assign csrd_n_c1uc_req = (counter == SET_CSRD_C1UC);
     
156. assign csrd_n_c1ia_req = (counter == SET_CSRD_C1IA);
     
157. assign csrd_n_c1ib_req = (counter == SET_CSRD_C1IB);
     
158. assign csrd_n_c1ic_req = (counter == SET_CSRD_C1IC);
     
159. 
     
160. assign csrd_n_c2ua_req = (counter == SET_CSRD_C2UA);
     
161. assign csrd_n_c2ub_req = (counter == SET_CSRD_C2UB);
     
162. assign csrd_n_c2uc_req = (counter == SET_CSRD_C2UC);
     
163. assign csrd_n_c2ia_req = (counter == SET_CSRD_C2IA);
     
164. assign csrd_n_c2ib_req = (counter == SET_CSRD_C2IB);
     
165. assign csrd_n_c2ic_req = (counter == SET_CSRD_C2IC);
     
166. 
     
167. 
     
168. assign data_c1ua_req = (counter == SET_DATA_C1UA);
     
169. assign data_c1ub_req = (counter == SET_DATA_C1UB);
     
170. assign data_c1uc_req = (counter == SET_DATA_C1UC);
     
171. assign data_c1ia_req = (counter == SET_DATA_C1IA);
     
172. assign data_c1ib_req = (counter == SET_DATA_C1IB);
     
173. assign data_c1ic_req = (counter == SET_DATA_C1IC);
     
174. 
     
175. assign data_c2ua_req = (counter == SET_DATA_C2UA);
     
176. assign data_c2ub_req = (counter == SET_DATA_C2UB);
     
177. assign data_c2uc_req = (counter == SET_DATA_C2UC);
     
178. assign data_c2ia_req = (counter == SET_DATA_C2IA);
     
179. assign data_c2ib_req = (counter == SET_DATA_C2IB);
     
180. assign data_c2ic_req = (counter == SET_DATA_C2IC);
     
181. 
     
182. 
     
183. assign fifo_data_req = (counter == SET_FIFO_DATA);
     
184. assign idle_req = (counter == SET_IDLE);
     
185. assign f_nrd[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA || cstate == DATA_C1UB || cstate == CSRDN_C1UB || cstate == DATA_C1UC || cstate == CSRDN_C1UC || cstate == DATA_C1IA || cstate == CSRDN_C1IA || cstate == DATA_C1IB || cstate == CSRDN_C1IB || cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ? f_nrd_reg[0] : 1'b1; 
     
186. assign f_ncs[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA || cstate == DATA_C1UB || cstate == CSRDN_C1UB || cstate == DATA_C1UC || cstate == CSRDN_C1UC || cstate == DATA_C1IA || cstate == CSRDN_C1IA || cstate == DATA_C1IB || cstate == CSRDN_C1IB || cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ? f_ncs_reg[0] : 1'b1; 
     
187. assign f_nrd[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA || cstate == DATA_C2UB || cstate == CSRDN_C2UB || cstate == DATA_C2UC || cstate == CSRDN_C2UC || cstate == DATA_C2IA || cstate == CSRDN_C2IA || cstate == DATA_C2IB || cstate == CSRDN_C2IB || cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ? f_nrd_reg[1] : 1'b1;
     
188. assign f_ncs[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA || cstate == DATA_C2UB || cstate == CSRDN_C2UB || cstate == DATA_C2UC || cstate == CSRDN_C2UC || cstate == DATA_C2IA || cstate == CSRDN_C2IA || cstate == DATA_C2IB || cstate == CSRDN_C2IB || cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ? f_ncs_reg[1] : 1'b1;
     
189. assign fifo_wr = ( /* cstate ==DATA_C1UA ||*/ cstate == DATA_C1UB || cstate == DATA_C1UC || cstate == DATA_C1IA || cstate == DATA_C1IB || cstate == DATA_C1IC || cstate == DATA_C2UA || cstate == DATA_C2UB || cstate == DATA_C2UC || cstate == DATA_C2IA || cstate == DATA_C2IB || cstate == DATA_C2IC ||cstate == FIFO_DATA ) ? fifo_wr_reg : 1'b0; 
     
190. 
     
191. 
     
192. 
     
193. always @ (posedge clk or negedge rst)
     
194.     if(!rst) 
     
195.         cstate <= IDLE;
     
196.     else
     
197.         cstate <= nstate;
     
198. 
     
199. always @ (cstate or fifo_data_req or csrd_n_c1ua_req or data_c1ub_req or csrd_n_c1uc_req or data_c1ia_req or data_c1ib_req or data_c1ic_req or csrd_n_c2ua_req or data_c2ub_req or csrd_n_c2uc_req or data_c2ia_req or data_c2ib_req or data_c2ic_req) 
     
200.     case (cstate)
     
201.         IDLE: 
     
202.             if(csrd_n_c1ua_req)
     
203.                 nstate <= CSRDN_C1UA;
     
204.             else
     
205.                 nstate <= IDLE;
     
206.          CSRDN_C1UA:
     
207.             if(data_c1ua_req)
     
208.                 nstate <= DATA_C1UA;
     
209.             else
     
210.                 nstate <= CSRDN_C1UA;
     
211.          DATA_C1UA:
     
212.             nstate <= DATA1_C1UA;
     
213.          DATA1_C1UA:
     
214.             if(csrd_n_c1ub_req)
     
215.                 nstate <= CSRDN_C1UB;
     
216.             else
     
217.                 nstate <= DATA1_C1UA;
     
218.          CSRDN_C1UB:
     
219.             if(data_c1ub_req)
     
220.                 nstate <= DATA_C1UB;
     
221.             else
     
222.                 nstate <= CSRDN_C1UB;
     
223.          DATA_C1UB:
     
224.             nstate <= DATA1_C1UB;
     
225.          DATA1_C1UB:
     
226.             if(csrd_n_c1uc_req)
     
227.                 nstate <= CSRDN_C1UC;
     
228.             else
     
229.                 nstate <= DATA1_C1UB;        
     
230.          CSRDN_C1UC:
     
231.             if(data_c1uc_req)
     
232.