We are using AM3352 Processor in one of our Product. In This product we have connected AM3352 Processor GPMC interface with TI-DSP 5501(HPI interface). TI DSP has NWait signal which is connected with the processor WAIT Pin.   We are configuring the Chip select which is connected with the TI-DSP in the asynchronous mode with Wait Pin Monitoring enable both for Read and write access with Low Polarity on GPMC wait Pin 1.   Now we are referring the data sheet "Sitara AM335X ARM@ Cortex -A8 Technical Reference Manual.pdf" -    Query: 1: In this Topic: "7.1.3.3.8.3.2" Wait Monitoring During an Asynchronous Read Access. In this Topic: "7.1.3.3.8.3.3" Wait Monitoring During an Asynchronous Write Access.   We have understand and derive the below mention Points.   1: During Asynchronous Read Access - wait pin monitoring is start from the Cycle and it will continuously check the wait pin monitoring till the least GPMC clock cycle  before the RDACCESSTIME completes. During this time GPMC module found the Wait Pin Low it will Freeze all the control signals (Address/Data/RD/CS) and this control signals are kept in that state till the Wait Pin goes high.   2: During Asynchronous Write Access - wait pin monitoring is start from the Cycle and it will continuously check the wait pin monitoring till the least GPMC clock cycle  before the WRACCESSTIME completes. During this time GPMC module found the Wait Pin Low it will Freeze all the control signals (Address/Data/RD/CS) and this control signals are kept in that state till the Wait Pin goes high.   Please confirm our understating Regarding the Wait Pin behavior. Any deviation in  this then explain the behavior in detailed.   Query: 2: In this Topic: "7.1.3.3.8.3.2" Wait Monitoring During an Asynchronous Read Access.  Below Lines are Mention: "When a delay larger then Two  GPMC clocks must be observed between wait-pin deactivation time and data valid time,an extra delay can be added between wait-pin deassertion time detection and effective data -capture time and the effective unlock of the CYCLETIME counter. This extra delay can be programmed in the GPMC_CONFIG1[19-18] WAITMONITORINGTIME field. The WAITMONITORINGTIME parameter does not delay the wait-pin active or inactive detection,nor does it modify the two GPMC clocks pipelined detection delay   Please clarify the above mention points. We are not able to understand the exact purpose of the GPMC_CONFIG1[19-18] WAITMONITORINGTIME parameter with the wait signal   Regards,     1. Yes, your understanding is correct.
2. WAITMONITORINGTIME will add extra delay time after the WAIT pin deasserts before data is captured.   Best Regards Biser