之前有过YDA174的设置经历，手册起来比较容易，但是为了以后遇到需要配置，这里将配置的方法写下，以备后续查阅

时钟域框图

1CLOCK CONTROL REGISTER设置（disable clock）

向地址0x4000写入0x0E bit： bit name： setting 3 CLKSRC 0：Direct from MCLK pin(default) 1: PLL clock [2:1] INFREQ[1:0] 00:256fs(default) 01:512fs 10:768fs 11:1024fs 0 COREN 0:core clock disabled(disabled) 1:Core clock enabled

2设置PLL(0x4002),输入频率8MHz～27MHz（六个寄存器需要burst写完）

主要是计算PLL的值
/* MCLK = 10 MHz R = 0100 = 4, N = 0x02 0x3C = 572, M = 0x02 0x71 = 625 PLL required output = 1024x48 KHz (PLLout) = 49.152 MHz PLLout/MCLK = 49.152 MHz/10 MHz = 4.9152 MHz = R + (N/M) = 4 + (572/625) */这里给的是MCLK输入是10MHz的设置值

3，待锁相完成后，使能时钟

PLL control register（的第一个bit，设置成1）；CLOCK control register设置成0x0F。
以下寄存器，只有在PLL稳定后存取才是可行的。

4.设置mixers, ADC's, DAC's, and amplifiers 接收立体声线路输入输出

AudioWriteToReg(R4_RECORD_MIXER_LEFT_CONTROL_0, 0x01); //enable mixer 1 AudioWriteToReg(R5_RECORD_MIXER_LEFT_CONTROL_1, 0x07); //unmute Left channel of line in into mxr 1 and set gain to 6 db AudioWriteToReg(R6_RECORD_MIXER_RIGHT_CONTROL_0, 0x01); //enable mixer 2 AudioWriteToReg(R7_RECORD_MIXER_RIGHT_CONTROL_1, 0x07); //unmute Right channel of line in into mxr 2 and set gain to 6 db AudioWriteToReg(R19_ADC_CONTROL, 0x13); //enable ADCs AudioWriteToReg(R22_PLAYBACK_MIXER_LEFT_CONTROL_0, 0x21); //unmute Left DAC into Mxr 3; enable mxr 3 AudioWriteToReg(R24_PLAYBACK_MIXER_RIGHT_CONTROL_0, 0x41); //unmute Right DAC into Mxr4; enable mxr 4 AudioWriteToReg(R26_PLAYBACK_LR_MIXER_LEFT_LINE_OUTPUT_CONTROL, 0x05); //unmute Mxr3 into Mxr5 and set gain to 6db; enable mxr 5 AudioWriteToReg(R27_PLAYBACK_LR_MIXER_RIGHT_LINE_OUTPUT_CONTROL, 0x11); //unmute Mxr4 into Mxr6 and set gain to 6db; enable mxr 6 AudioWriteToReg(R29_PLAYBACK_HEADPHONE_LEFT_VOLUME_CONTROL, 0xFF);//Mute Left channel of HP port (LHP) AudioWriteToReg(R30_PLAYBACK_HEADPHONE_RIGHT_VOLUME_CONTROL, 0xFF); //Mute Right channel of HP port (LHP) //AudioWriteToReg(R31_PLAYBACK_LINE_OUTPUT_LEFT_VOLUME_CONTROL, 0xE6); //set LOUT volume (0db); unmute left channel of Line out port; set Line out port to line out mode //AudioWriteToReg(R32_PLAYBACK_LINE_OUTPUT_RIGHT_VOLUME_CONTROL, 0xE6); // set ROUT volume (0db); unmute right channel of Line out port; set Line out port to line out mode AudioWriteToReg(R31_PLAYBACK_LINE_OUTPUT_LEFT_VOLUME_CONTROL, 0xFE); //set LOUT volume (0db); unmute left channel of Line out port; set Line out port to line out mode AudioWriteToReg(R32_PLAYBACK_LINE_OUTPUT_RIGHT_VOLUME_CONTROL, 0xFE); // set ROUT volume (0db); unmute right channel of Line out port; set Line out port to line out mode AudioWriteToReg(R35_PLAYBACK_POWER_MANAGEMENT, 0x03); //enable left and right channel playback (not sure exactly what this does...) AudioWriteToReg(R36_DAC_CONTROL_0, 0x03); //enable both DACs AudioWriteToReg(R58_SERIAL_INPUT_ROUTE_CONTROL, 0x01); //Connect I2S serial port output (SDATA_O) to DACs AudioWriteToReg(R59_SERIAL_OUTPUT_ROUTE_CONTROL, 0x01); //connect I2S serial port input (SDATA_I) to ADCs AudioWriteToReg(R65_CLOCK_ENABLE_0, 0x7F); //Enable clocks AudioWriteToReg(R66_CLOCK_ENABLE_1, 0x03); //Enable rest of clocks

5类似于4，如果是headPhone输入输出则设置如下：

AudioWriteToReg(R17_CONVERTER_CONTROL_0, 0x05);//48 KHz AudioWriteToReg(R64_SERIAL_PORT_SAMPLING_RATE, 0x05);//48 KHz AudioWriteToReg(R19_ADC_CONTROL, 0x13); AudioWriteToReg(R36_DAC_CONTROL_0, 0x03); AudioWriteToReg(R35_PLAYBACK_POWER_MANAGEMENT, 0x03); AudioWriteToReg(R58_SERIAL_INPUT_ROUTE_CONTROL, 0x01); AudioWriteToReg(R59_SERIAL_OUTPUT_ROUTE_CONTROL, 0x01); AudioWriteToReg(R65_CLOCK_ENABLE_0, 0x7F); AudioWriteToReg(R66_CLOCK_ENABLE_1, 0x03); AudioWriteToReg(R4_RECORD_MIXER_LEFT_CONTROL_0, 0x01); AudioWriteToReg(R5_RECORD_MIXER_LEFT_CONTROL_1, 0x05);//0 dB gain AudioWriteToReg(R6_RECORD_MIXER_RIGHT_CONTROL_0, 0x01); AudioWriteToReg(R7_RECORD_MIXER_RIGHT_CONTROL_1, 0x05);//0 dB gain AudioWriteToReg(R22_PLAYBACK_MIXER_LEFT_CONTROL_0, 0x21); AudioWriteToReg(R24_PLAYBACK_MIXER_RIGHT_CONTROL_0, 0x41); AudioWriteToReg(R26_PLAYBACK_LR_MIXER_LEFT_LINE_OUTPUT_CONTROL, 0x03);//0 dB AudioWriteToReg(R27_PLAYBACK_LR_MIXER_RIGHT_LINE_OUTPUT_CONTROL, 0x09);//0 dB AudioWriteToReg(R29_PLAYBACK_HEADPHONE_LEFT_VOLUME_CONTROL, 0xE7);//0 dB AudioWriteToReg(R30_PLAYBACK_HEADPHONE_RIGHT_VOLUME_CONTROL, 0xE7);//0 dB AudioWriteToReg(R31_PLAYBACK_LINE_OUTPUT_LEFT_VOLUME_CONTROL, 0xE6);//0 dB AudioWriteToReg(R32_PLAYBACK_LINE_OUTPUT_RIGHT_VOLUME_CONTROL, 0xE6);//0 dB

6，I2S输入输出音频数据

接着就是I2S驱动输入输出数据了。
7.遇到的问题 zynq的FCLK并未输出10MHz时钟。