1.什么是prefetch?
prefetch 字面意思就是预取,在DDR memory chip里面用的一个技术方案。DDR1 采用2n prefetch,DDR2采用4n prefetch,DDR3采用8n prefetch。所谓的n指的是chip对外的I/O width。以DDR3为例,它的IO gating buffer与FIFO的接口宽度是FIFO与外部IO的接口宽度的8倍。对于8bits位宽的 DDR3 MEMORY chip,为了满足8n prefetch,IO gating buffer的宽度要达到64 bits的位宽。
2.prefetch有什么好处?
在不改变memory内部 cell array架构的情况下,通过改变接口技术,最大化数据传输速率。这是prefetch的目的,也是它相对于SDR的优势所在。DDR3为例,DDR3 1600的数据传输速率。采用8n prefetch,它的内部core frequency仍然可以保持在100Mhz。
3.prefetch是怎么实现的?
简单的说,就是在read的时候,DDR chip慢送,controller快取,在write的时候,controller快送,DDR chip慢取。结构上,就是一个双口FIFO来实现的prefetch。
在谈cell内、外数据位宽时,不得不谈谈两个时钟域的问题,这两个时钟域就是cell外部时钟域DQS和内部时钟域CLK;针对2N倍的prefetch,对外部时钟来说(DQS),由于其采用上下边沿采样,这样也就意味着,一个DQS周期可以完成两倍的数据取样,获得的数据放在FIFO里面;当FIFO满后,由内部时钟域(CLK)的时钟将数据从FIFO取走。注意,由于cell内部的FIFO较常见的FIFO不同,其没有溢出标志位,所以,其需要内部时钟与外部时钟满足一定的约束关系,而且,由于prefetch是2N倍,所以,FIFO满的时候一定是以DQS下降沿采样结束的。(说到着,相信会有很多人马上就会心一笑,哦,DRAM
cell的数据手册中对DQS的下降沿与clk有一个建立时间和保持时间的约束要求的目的原来是这样:)(摘抄自网络http://www.pcbsi.com/bbs/archiver/tid-410.html)
Since DDR already transfers data on both the rising and falling edges of a clock cycle, how does DDR2 double the bandwidth yet again? The answer lies in the I/O buffer frequency, which is doubled with DDR2.
The memory controller in our systems only deal with the I/O buffer on the memory chip. To double the data from the memory array to the I/O buffer, DDR2 utilizes a “4-bit prefetch” as opposed to the “2-bit prefetch” with DDR. This means that 4 bits of data
are moved from the memory array to the I/O buffer per data line each core clock cycle.
The
core clock cycle here refers to the cycle time of the memory array, and the frequency of the memory array is half that of the I/O buffer and 1/4 of the data rates. Take DDR2 800 for example: it has an 800MHz data rate, the I/O buffer works at 400MHz,
and the core frequency of the memory array is only 200MHz. The core frequency remains the same as DDR400. However, the DDR400 I/O buffer operates at 200MHz. The time of “a core cycle” is therefore the same whether it is DDR400 or DDR2 800.
增加一个URL:
http://www.pjtime.com/2010/4/75177245.shtml