最近试着调试DM3730的DSP64+       现把调试结果如下：      版本CCS4.24    平台SBC3730 1.  首先连接cortexA8 2.  其次 Scripts->OMAP3EVM 这里边有个startup(),如果没有硬件问题，console会出现时钟设置，使omap得到时钟等(DDR设置可能要改变)：如下 Cortex_A8_0: GEL Output: Wait In Reset is enabled through GEL. Cortex_A8_0: GEL Output: System Reset has been issued through GEL. Cortex_A8_0: GEL Output: Target has been reset
Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Locking CORE DPLL
Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
Cortex_A8_0: GEL Output:  SystemClock = 26.0 MHz
Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 332
Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 25
Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 664.0 MHz
Cortex_A8_0: GEL Output:  CORE_CLK = 332.0 MHz
Cortex_A8_0: GEL Output:  L3_CLK = 166.0 MHz
Cortex_A8_0: GEL Output: MM02: mDDR Micron MT46H32M32LFCM - 1024 Mbit(128MB) on CS0, 8M x 32bit x 4Banks
Cortex_A8_0: GEL Output: Waiting for SDRC DLL to lock...
Cortex_A8_0: GEL Output: SDRC DLL successfully locked
Cortex_A8_0: GEL Output: common_sdram_init() completed
Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Micron_MT46H32M32LFCM completed
Cortex_A8_0: GEL Output:
OMAP3EVM start sequence has completed. 3. 运行 Scripts->IVA2200_Startup->IVA22_GEM_Startup.  使DSP从复位状态解放 4.  最后连接C6400PLUS. connect target.