• digital data can be processed and transmitted more efficiently and reliably than analog data.
• digital form can be stored more compactly and reproduced with greater accuracy and clarity than is possible when it is in analog form.
• Noise (unwanted voltage fluctuations) does not affect digital data nearly as much as it does analog signals
模拟电子系统(An Analog System)
使用数字方法和模拟方法的系统。(A System Using Digital and Analog Methods)
其中,ADC:数模转换器;DSP:数字信号处理;CDA:模数转换
二进制数、逻辑电平和数字波形(Binary Digits、Logic Levels、and Digital Waveforms)
先介绍一下数字波形中的一些概念:
The Pulse:leading edge (also called rising edge ):occurs first at time t0
falling edge (also called tralling edge):occurs last at time t1
The picture above shows us a ideal pulses because the rising and falling edges are assumed to change in zero time (instantaneously)
The picture below shows us a nonideal pulse .(always resulted by RC circuit ) rise time(tr) fall time(tf) amplitude
**pulse width **:is a measure of the duration of the pulse and is often defined as the tiem intercal between the 50%points on the rising and falling edges ,as indicated in Figure below
Waveform Characteristics(波形特性)
period:周期
frequency:频率
duty cycle:占空比
数字波形携带二进制信息(A Digital Waveform Carries Binary Information)
时钟(clock):在数字系统中,所有的波形都与一个基本时序波形同步,称之为时钟。每个脉冲之间的间隔(周期)等于一个位时间(the period or called the Bit time)。
例题:
(a) Determine the total time required to serially transfer the eight bits contained in waveform A of Figure 1–14, and indicate the sequence of bits. The left-most bit is the first to be transferred. The 1 MHz clock is used as reference. (b) What is the total time to transfer the same eight bits in parallel?
解:时钟频率是1MHz,所以周期就可以得到:
即传送以为需要一微秒,则传输8个位需要8微秒
而并行传送8各位需要1微秒的时间
基本逻辑功能(Basic Logic Functions)
组合和顺序逻辑功能(Combinational and Sequential Logic Functions)
累了,,,过两天再整理(我欣喜的发现CSDN可以全文修改哈哈哈哈)
adc——dsp——cdaf
paratic golical正逻辑
当然同时也有负逻辑这个东西
在数字信号传输过程中是有电压波动的,但是因为high/low的划定是有其一贯额范围的,所以有相当的容错性。如果实在low到high之间,就会成为invalid,即不存在
digital waveforms:数字波形,
0——1——0:正脉冲;
1——0——1:负脉冲
rising edge和falling edge都是一个时间点
正脉冲占总周期的比率叫做duty cycle
cpu的clock
时序图:timing diagrams
0100
0011这种如何区分两个1呢?
所以要有一个clock,一个clock周期一个数据
有些孩纸啊上升沿河下降沿的地方传输数据
在上面时候读数据最稳定?所以一般在clock的下降沿读数据比较准确
data can be transmitted by either serial transfer(ex.usb)or parallel transfer
数据串行传输或者并行传输
串行不一定有时钟
慢切斯特编码
也可以双方约定好一个bit的长度
串口的数据传输方式就是约定好传输的bit常数和bit开始的时间点
但是并行一定有clock