电源

PXA310系统电源管理

2019-07-14 03:45发布

站内文章 / 电源技术
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XA310系统电源： http://blog.ednchina.com/canback/180197/message.aspx   PXA3xx_Design_Guide.pdf     - chapter 3: Minimize power consumption

1. PXA3xx电源管理的特点：     - Five reset resource: Power-on, Hardware, Watchdog, General-purpose I/O(GPIO),         and Reset upon exit from S2/D3/C4 and S3/D4/C4 modes(S3/D4/C4 is only used         upon initial power up).
    - Wake up from low-power operation is supported by available peripherals
    - Supported speeds are: 806MHz, 624MHz, 416MHz, 208MHz, 104MHz        (Only pxa32x support 806MHz)
    - Programmable frequency-change capability, with turbo settings without         requiring the PLL to re-lock
    - Seven power modes to control power consumption: S0/D0/C0 (normal using either         run and turbo clock configurations), S0/D0CS/C0 (run operation with ring         oscillator operation at 60MHz), S0/D0/C1 (core idle), S0/D1/C2 (standby         with LCD refresh), S0/D2/C2 (standby), S2/D3/C4 (sleep), and S3/D4/C4 (deep         sleep)
    - Dedicated programmable I2C-based externel regulator interface to power         management ICs
2. Pin descriptions and control
    - each of multi-function pin can be configured to one of five states:           Output driven high           Output driven low           Output high inpendance           Input pulled high           Input pulled low
    - the pin unit also contains register to configure the output drive strenth of         individual pins when configured as outputs.
    - all multi-function pins support configuration as a software-managed GPIO         channel, which can be programmed as output or an input that can serve as an         interrupt source. Many pins can also generate wake-up events to bring the         processor out of the S0/D1/C2, S0/D2/C2, S2/D3/C4 and S3/D4/C4 low-power         mode
    - 每一个GPIO pin 都可以用MFPR去配置该pin的功能。   3. GPIO     - At the assertion of all resets, all 128 ports are configured as inputs and         remain inputs until they are configured either by boot processes or by user         software.       - GPDRx: GPIO pin direction register, 设置GPIO的方向，输入或输出。
    - GPSRx: GPIO pin output set register, 当设为输出时，用这个来输出1
     - GPCRx: GPIO pin output clear register, 当设为输出时，用这个来输出0        GPSRx和GPCRx无论GPIO设置为输入和输出时都可以设置，只不过只有设为输出时，该设置才起作用。
    - GRERx: 输入时，配置为检测上升沿
     - GFERx: 输入时，配置为检测下降沿     - GEDRx: 读出具体是触发时是什么沿       - GPLRx: 每个GPIO的直，1或0。无论是在输入还是输出状态    
    - GSDRx/G CDRx: set或者clear the bits in GPDRx.
    - GSRERx/GCRERx: set/clear the bits in GRERx.       - GSFERx/GCFERx: set/clear the bits in GFERx.   4. Power management.       - Power management sw enters every power modes by writing to the Core PWRMODE         Register(CP14 Register 7) and exitts these modes through a wakeup event.       - S0/D0/C1: Core Idle mode saves power by stopping the core clock and retaining        core state while allowing all other units to operate normally. To enter this        mode, sw must write a 0x01 to the M field in the CP14. Any enabled interrupt        can wakeup the core from idle mode, regardless of the state of the Interrupt        Controller Mask Register(ICMR). If normal interrupt-masking behavior is        required, this feature can be disabled by setting the Disable Idle Mask(DIM)        bit in the Interrupt Controller Register(ICCR). If the DIM bit is cleared        and an idle mode wakeup from a given unit is not wanted, the unit interrupt        must be disabled at the unit level.       - S0/D0CS/C0: Ring Oscillator Mode. An internal ring oscillator is used to        clock the processor and system for low-power operation.  The ring oscillator        can be used for MP3 Playback mode. In this mode, the core PLL and system PLL        can be turned off to save power. Because of frequency limitations, not all        peripherals can run. The core runs at 60MHz from the ring Oscillator, the        DDR runs at up to 30MHz, and internal SRAM runs at 60MHz.       - Phone在开机后基本上都在S0的状态，DDR不掉电。       - Power Mode Clocking: P181
        PXA3xx_Processor_Family_Developer_Manual_Vol[1]._I_Version_1.0_Rev._C.pdf
    - The ACCU contains two clock-enable registers:        D0CKEN_A - D0 Mode Clock Enable Register A        D0CKEN_B - D0 Mode Clock Enable Register B        当处理器处于S0/D0/C0运行模式时，这两个寄存器中的CKEN位用来使能/关闭相应的外设时钟       - Operation point & Core Frequency:          Set in ACCR register: XL, XN           Core frequency = 13MHz * ACCR[XL] * ACCR[XN]        There are two ways
         
       

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