UNS的目的就是检查设计公司提交的网表是否合乎规则，确保输入到后端公司的网表是干净的。
进行网表检查的步骤分为两步：1.读入网表，timing/power library .lib flow.tcl
2.运行同时检查报告
Check Design Content and Syntax
–Notify error command usage
–Notify syntax error (e.g. when parsing a gate-level netlist or a dot library file)
–Notify unmapped logic (e.g. instance that fail to link with dot library)
–Notify irregular design content (e.g. lengthy module name or signal name)
–Notify assign statement
–Notify modules referenced multiple times
–Notify connection mismatch (e.g. inconsistency on bus width)
–Notify redundant signals or logics
–Notify inconsistency between netlist and dot library
–Notify ambiguous module name (e.g. case ambiguity)
–Notify ambiguous port connection (e.g. input port connect to output pin)
–Notify power management cell usage
Report Design Specification
–Report referenced module (for I/O pad, hard macro and core cells)
–Report macro cell instance (memory or hard macro)
–Report boundary port specification (connectivity and I/O pad utilization for chip level)
–Report fan-out distribution (complexity of internal wire)
–Report design hierarchy (for module reference, instance count, equivalent gate count and sequential elements for DFT purpose)
–Report conditional leakage power (according to the specified case analysis)
–Report datasheet power (for leakage and internal power)
–Report data profile according to library set
Check Engineering Rule
–Check memory block (enumerated memory instances, incomplete clock gating)
–Check spare cell (illegal specification,profiling and don’t touch SDC constraint)
–Check sub design block (large sub designs, unmapped logics, assign statement)
–Check high fan-out net (distinguish into non-clock tree and clock tree network)
–Check timing arcs (combinational feedback, lengthy path and possible generated clock)
–Check cell connectivity (floating input/bi-direction, multiple drivers)
–Check port connectivity (floating input/bi-direction, ambiguous port connection)
–Check pad cell (floating, illegal multiple bond pads, multiple drivers, use internally)
–Check constant (signals tied to 1’b0 /1’b1 and signals driven by tie-high/tie-low cells)
–Check clock domain (enumerated clock roots, non-driven clock pins, profiling of clock tree cells and detail report on clock tree cells)
–Check power management cell (isolation, level shifter, switch and retention flip-flop)
–Check analog path (enumerated analog instances, digital cells inserted on analog path)
•Report Design Summary
–A summary report summarizes the profile of design contents, main findings of possible errors, complexity evaluation and leakage power consumption.
主要的关注点：
1.输入输出端口多驱动/多扇出，悬空，没有连接到pad
2.模块扇出较多，可能存在后端无法布线的情况。
3.存储是否使用门控单元以降低功耗
4.spare cell的使用
5.模块最大门数
6.cell连接是否正确，pad连接是否正确
7.常值网络连接是否正常
8.时钟网络连接是否正常
9.模拟cell是否处理正常
10.对于库中不能使用的cell是否出现
11.命名规则是否符合规则
网表的检查主要是报告涉及规范和是否符合工程规则，
第一保证符合前端涉及的基本准则，
第二保证后端设计的规则标准