-
yconnor
发布于
DSP
-
0评论
-
13374次浏览
-
1297人收藏
-
2019-07-13 17:44
1.Compile coreB beare-metal in CCES
1.1 import coreB project
1.2 add sdramcplb entries to startup_ldr/app_cplbtab.c
/*SDRAM Memory */
{0x0,(ENUM_DCPLB_DATA_64MB | CPLB_DNOCACHE)},
{0x4000000,(ENUM_DCPLB_DATA_64MB ...