在ADS平台下，对AT91R40008进行FLASH程序引导，目前问题运行，现在把BOOT_FLASH.S 分享给大家，程序如下 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;  boot from FLASH: initialization       ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 GET option_boot.h
 GET memcfg.h ;interrupt controller
INTPND EQU 0x01e00004
INTMOD EQU 0x01e00008
INTMSK EQU 0x01e0000c
I_ISPR EQU 0x01e00020
I_CMST EQU 0x01e0001c
I_PMST EQU 0x01e00014 ;Watchdog timer
WTCON EQU 0x01d30000 ;Clock Controller
PLLCON EQU 0x01d80000
CLKCON EQU 0x01d80004
LOCKTIME EQU 0x01d8000c ;Memory Controller
REFRESH EQU 0x01c80024 ;BDMAhdog timer
BDIDES0 EQU 0x1f80008
BDIDES1 EQU 0x1f80028 ;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0 ;port config register
PCONA EQU 0x01d20000
PCONB EQU 0x01d20008
PCONC EQU 0x01d20010 ;mem controller
BWSCON EQU 0x01c80000
 MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
 sub sp,sp,#4   ;decrement sp(to store jump address)
 stmfd sp!,{r0}   ;PUSH the work register to stack(lr does't push because it return to original address)
 ldr r0,=$HandleLabel ;load the address of HandleXXX to r0
 ldr r0,[r0]   ;load the contents(service routine start address) of HandleXXX
 str r0,[sp,#4]   ;store the contents(ISR) of HandleXXX to stack
 ldmfd sp!,{r0,pc}  ;POP the work register and pc(jump to ISR)
 MEND  MACRO
$HandlerLabel VHANDLER $HandleLabel
$HandlerLabel
 sub sp,sp,#4
 stmfd sp!,{r0}
 ldr r0,=I_ISPR ;INTMSK work-around
 ldr r0,[r0]
 cmp r0,#0x0
 beq %F0
 ldr r0,=$HandleLabel
 ldr r0,[r0]
 str r0,[sp,#4]
 ldmfd sp!,{r0,pc}
0  stmfd sp!,{r1}
 ldr r0,=I_PMST
 ldr r1,[r0]
 str r1,[r0]
 ldmfd sp!,{r0,r1}
 add sp,sp,#4
 subs pc,lr,#4
 MEND
 
 
 IMPORT |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
 IMPORT |Image$$RW$$Base|  ; Base of RAM to initialise
 IMPORT |Image$$ZI$$Base|  ; Base and limit of area
 IMPORT |Image$$ZI$$Limit|  ; to zero initialise   ;IMPORT main    ; The main entry of mon program ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;  coding area
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  AREA boot,CODE,READONLY
 ENTRY  b ResetHandler   ;system init
 b HandlerUndef   ;handlerUndef
 b HandlerSWI   ;SWI interrupt handler
 b HandlerPabort  ;handlerPAbort
 b HandlerDabort  ;handlerDAbort
 b .    ;handlerReserved
 b HandlerIRQ
 b HandlerFIQ
 ;*** IMPORTANT NOTE ***
 ;If the H/W vectored interrutp mode is enabled, The above two instruction should
 ;be changed like below, to work-around with H/W bug of S3C44B0X interrupt controller.
 ;If INTCON I,F bit is changed, this case may be occurred.
 ; b HandlerIRQ -> subs pc,lr,#4
 ; b HandlerIRQ -> subs pc,lr,#4
 
VECTOR_BRANCH
 ldr pc,=HandlerEINT0 ;mGA H/W interrupt vector table
 ldr pc,=HandlerEINT1 ;
 ldr pc,=HandlerEINT2 ;
 ldr pc,=HandlerEINT3 ;
 ldr pc,=HandlerEINT4567 ;
 ldr pc,=HandlerTICK ;mGA
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 
 ldr pc,=HandlerZDMA0 ;mGB
 ldr pc,=HandlerZDMA1 ;
 ldr pc,=HandlerBDMA0 ;
 ldr pc,=HandlerBDMA1 ;
 ldr pc,=HandlerWDT ;
 ldr pc,=HandlerUERR01 ;mGB
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 
 ldr pc,=HandlerTIMER0 ;mGC
 ldr pc,=HandlerTIMER1 ;
 ldr pc,=HandlerTIMER2 ;
 ldr pc,=HandlerTIMER3 ;
 ldr pc,=HandlerTIMER4 ;
 ldr pc,=HandlerTIMER5 ;mGC
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 
 ldr pc,=HandlerURXD0 ;mGD
 ldr pc,=HandlerURXD1 ;
 ldr pc,=HandlerIIC ;
 ldr pc,=HandlerSIO ;
 ldr pc,=HandlerUTXD0 ;
 ldr pc,=HandlerUTXD1 ;mGD
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 
 ldr pc,=HandlerRTC ;mGKA
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 
 ldr pc,=HandlerADC ;mGKB
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 ldr pc,=HandlerDef
 LTORG
 
HandlerFIQ  HANDLER HandleFIQ
HandlerIRQ  HANDLER HandleIRQ
HandlerUndef  HANDLER HandleUndef
HandlerSWI  HANDLER HandleSWI
HandlerDabort  HANDLER HandleDabort
HandlerPabort  HANDLER HandlePabort ;The following is used for the vectored interrupt.
HandlerADC  VHANDLER HandleADC
HandlerRTC  VHANDLER HandleRTC
HandlerUTXD1  VHANDLER HandleUTXD1
HandlerUTXD0  VHANDLER HandleUTXD0
HandlerSIO  VHANDLER HandleSIO
HandlerIIC  VHANDLER HandleIIC
HandlerURXD1  VHANDLER HandleURXD1
HandlerURXD0  VHANDLER HandleURXD0
HandlerTIMER5  VHANDLER HandleTIMER5
HandlerTIMER4  VHANDLER HandleTIMER4
HandlerTIMER3  VHANDLER HandleTIMER3
HandlerTIMER2  VHANDLER HandleTIMER2
HandlerTIMER1  VHANDLER HandleTIMER1
HandlerTIMER0  VHANDLER HandleTIMER0
HandlerUERR01  VHANDLER HandleUERR01
HandlerWDT  VHANDLER HandleWDT
HandlerBDMA1  VHANDLER HandleBDMA1
HandlerBDMA0  VHANDLER HandleBDMA0
HandlerZDMA1  VHANDLER HandleZDMA1
HandlerZDMA0  VHANDLER HandleZDMA0
HandlerTICK  VHANDLER HandleTICK
HandlerEINT4567 VHANDLER HandleEINT4567
HandlerEINT3  VHANDLER HandleEINT3
HandlerEINT2  VHANDLER HandleEINT2
HandlerEINT1  VHANDLER HandleEINT1
HandlerEINT0  VHANDLER HandleEINT0 HandlerDef ;INTMSK work-around
 stmfd sp!,{r0,r1}
 ldr r0,=I_PMST
 ldr r1,[r0]
 str r1,[r0]
 ldmfd sp!,{r0,r1}
 subs pc,lr,#4
IsrIRQ
 sub sp,sp,#4 ;reserved for PC
 stmfd sp!,{r8-r9}
 ldr r9,=I_ISPR
 ldr r9,[r9]
 cmp r9, #0x0 ;In some case, I_ISPR may be 0.
 beq %F2
 mov r8,#0x0
0
 movs r9,r9,lsr #1
 bcs %F1
 add r8,r8,#4
 b %B0
1
 ldr r9,=HandleADC
 add r9,r9,r8
 ldr r9,[r9]
 str r9,[sp,#8]
 ldmfd sp!,{r8-r9,pc}
2
 ldr r8,=I_PMST ;INTMSK work-around.
 ldr r9,[r8]
 str r9,[r8]
 ldmfd sp!,{r8-r9}
 add sp,sp,#4
 subs pc,lr,#4
IsrFIQ
 sub sp,sp,#4 ;reserved for PC
 stmfd sp!,{r8-r9}
 ldr r9,=I_ISPR
 ldr r9,[r9]
 cmp r9, #0x0 ;In some case, I_ISPR may be 0.
 beq %F2
 mov r8,#0x0
0
 movs r9,r9,lsr #1
 bcs %F1
 add r8,r8,#4
 b %B0
1
 ldr r9,=HandleADC
 add r9,r9,r8
 ldr r9,[r9]
 str r9,[sp,#8]
 ldmfd sp!,{r8-r9,pc}
2
 ldr r8,=I_PMST ;INTMSK work-around.
 ldr r9,[r8]
 str r9,[r8]
 ldmfd sp!,{r8-r9}
 add sp,sp,#4
 subs pc,lr,#4
  
 
;****************************************************
;* START         *
;****************************************************
ResetHandler
    ldr     r0,=WTCON     ;watch dog disable
    ldr     r1,=0x0   
    str     r1,[r0]     ldr     r0,=INTMSK
    ldr     r1,=0x07ffffff  ;all interrupt disable
    str     r1,[r0]     ;****************************************************
    ;* Set clock control registers   *
    ;****************************************************
    ldr r0,=LOCKTIME
    ldr r1,=0xfff
    str r1,[r0]    
    ldr r0,=PLLCON    ;temporary setting of PLL
    ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) ;Fin=10MHz,Fout=60MHz
    str r1,[r0]
    ldr r0,=CLKCON  
    ldr r1,=0x7ff8     ;All unit block CLK enable 
    str r1,[r0]     ;****************************************************
    ;* Port Initialization    *
    ;****************************************************
    ldr r0,=PCONA
    ldr r1,=0x3ff
    str r1,[r0]   ;config GPIOA as addr. bus
   
    ldr r0,=PCONB
    ldr r1,=0x7ff
    str r1,[r0]   ;config GPIOB as mem controller interface
   
    ldr r0,=PCONC
    ldr r1,=0xaaaaaaaa
    str r1,[r0]   ;config GPIOC as data bus high bits     ;****************************************
    ;*  change BDMACON reset value for BDMA *  
    ;****************************************
    ldr r0,=BDIDES0      
    ldr r1,=0x40000000   ;BDIDESn reset value should be 0x40000000 
    str r1,[r0]     ldr r0,=BDIDES1     
    ldr r1,=0x40000000   ;BDIDESn reset value should be 0x40000000 
    str r1,[r0]
       ;****************************************************
    ;* Set memory control registers   *  
    ;****************************************************
    ldr     r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr     r0,=BWSCON   ;memory controller
    stmia   r0,{r1-r13}
 
    ;****************************************************
    ;* Clear LED display        *  
    ;****************************************************
    ldr     r0,=0x02000000
    ldr  r1,=0x0
    str  r1,[r0]
   
 ldr  r0,=0x1d20040 ;GPOIOG
 ldr  r1,=0xff55  ;
 str  r1,[r0]
 ldr  r0,=0x1d20044
 ldr  r1,=0xfe  ;light D4
 str  r1,[r0]     ;****************************************************
    ;* Initialize stacks    *
    ;****************************************************
    ;ldr     sp, =SVCStack ;
    ;bl     InitStacks
    mrs     r0,cpsr
    bic     r0,r0,#MODEMASK
    orr     r1,r0,#UNDEFMODE|NOINT
    msr     cpsr_cxsf,r1   ;UndefMode
    ldr     sp,=UndefStack
 
    orr     r1,r0,#ABORTMODE|NOINT
    msr     cpsr_cxsf,r1       ;AbortMode
    ldr     sp,=AbortStack     orr     r1,r0,#IRQMODE|NOINT
    msr     cpsr_cxsf,r1       ;IRQMode
    ldr     sp,=IRQStack
 
    orr     r1,r0,#FIQMODE|NOINT
    msr     cpsr_cxsf,r1       ;FIQMode
    ldr     sp,=FIQStack     orr     r1,r0,#SVCMODE|NOINT
    msr     cpsr_cxsf,r1       ;SVCMode
    ldr     sp,=SVCStack     ;****************************************************
    ;* Setup IRQ handler    *
    ;****************************************************
    ldr     r0,=HandleIRQ  ;This routine is needed
    ldr     r1,=IsrIRQ   ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c ???
    str     r1,[r0]     ldr     r0,=HandleFIQ  ;
    ldr     r1,=IsrFIQ   ;
    str     r1,[r0]
   
   
 ;***************************************************
 ; END
 ;***************************************************
 ;BL  main     ; jump to C program
 ;BL  __main  ;
 ldr  pc,=0x0d000000
 B .        
    LTORG SMRDATA DATA
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized.                     *
;*****************************************************************  DCD 0x22222220 ;Bank0=OM[1:0], Bank1~Bank7=32bit  DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
 DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
 DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
 DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
 DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
 DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
;"SDRAM"
 DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
 DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7  DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
 DCD 0x17   ;SCLK power down mode, BANKSIZE 16MB/16MB
 DCD 0x20   ;MRSR6 CL=2clk
 DCD 0x20   ;MRSR7  ALIGN  AREA RamData, DATA, READWRITE
   ^ (_ISR_STARTADDRESS-0x500) ;0x500 = 256*5  _ISR_STARTADDRESS = 0xdff_ff00
    
UserStack # 256 ;c1(c7)ffa00
SVCStack # 256 ;c1(c7)ffb00
UndefStack # 256 ;c1(c7)ffc00
AbortStack # 256 ;c1(c7)ffd00
IRQStack # 256 ;c1(c7)ffe00
FIQStack # 0 ;c1(c7)fff00   ^ _ISR_STARTADDRESS
  
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4 ;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
HandleSIO # 4
HandleIIC # 4
HandleURXD1 # 4
HandleURXD0 # 4
HandleTIMER5 # 4
HandleTIMER4 # 4
HandleTIMER3 # 4
HandleTIMER2 # 4
HandleTIMER1 # 4
HandleTIMER0 # 4
HandleUERR01 # 4
HandleWDT # 4
HandleBDMA1 # 4
HandleBDMA0 # 4
HandleZDMA1 # 4
HandleZDMA0 # 4
HandleTICK # 4
HandleEINT4567 # 4
HandleEINT3 # 4
HandleEINT2 # 4
HandleEINT1 # 4
HandleEINT0 # 4         END 此帖出自小平头技术问答