没用过这个。你翻翻同系列其他器件的这个寄存器看看

我怎么感觉翻译的是，当CEOUT为0时，这个寄存器和tap 0寄存器的值一样。

dirtwillfly 发表于 2015-11-19 17:07
没用过这个。你翻翻同系列其他器件的这个寄存器看看

看了,都是一样的描述,

1. The voltage reference generator is used to generate VREF, which can be applied to either comparator
   
2. input terminal. The CEREF1x (VREF1) and CEREF0x (VREF0) bits control the output of the voltage
   
3. generator. The CERSEL bit selects the comparator terminal to which VREF is applied. If external signals
   
4. are applied to both comparator input terminals, the internal reference generator should be turned off to
   
5. reduce current consumption. The voltage reference generator can generate a fraction of the device V
   
6. CC
   
7. or
   
8. of the voltage reference of the integrated precision voltage reference source. Vref1 is used while CEOUT
   
9. is 1, and Vref0 is used while CEOUT is 0. This allows the generation of a hysteresis without using external
   
10. components

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说的是实现滞回功能,有点难以理解,不过不用这么高级的 功能,先不管它了.

xyz549040622 发表于 2015-11-20 08:06
我怎么感觉翻译的是，当CEOUT为0时，这个寄存器和tap 0寄存器的值一样。

这个tap是带的意思. 反正写的不规范,一下用ladder来表示,一下用string来表示,一下又用tap来表示,搞的都晕了.