两个不同的结构体吧  
{
    int x;
    volatile struct MBOX *pMbox;
    volatile union CANLAM_REG *pLam;
    /* Create a shadow register structure for the CAN control registers. This is     needed, since only 32-bit access is allowed to these registers. 16-bit access     to these registers could potentially corrupt the register contents or return     false data. This is especially true while writing to/reading from a bit     (or group of bits) among bits 16 - 31 */    struct ECAN_REGS ECanaShadow;    EALLOW;
    /* Enable internal pull-up for the selected CAN pins */    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.    // Comment out other unwanted lines.
     GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;    // Enable pull-up for GPIO30 (CANRXA)    // GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;  // Enable pull-up for GPIO18 (CANRXA)     GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;    // Enable pull-up for GPIO31 (CANTXA)    // GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;  // Enable pull-up for GPIO19 (CANTXA)    /* Set qualification for selected CAN pins to asynch only */    // Inputs are synchronized to SYSCLKOUT by default.
    // This will select asynch (no qualification) for the selected pins.
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)    //  GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)    /* Configure eCAN-A pins using GPIO regs*/
    // This specifies which of the possible GPIO pins will be eCAN functional pins.
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;// Configure GPIO30 for CANRXA operation     //  GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;// Configure GPIO18 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;// Configure GPIO31 for CANTXA operation
    //  GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;// Configure GPIO19 for CANTXA operation
    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */    // HECC mode also enables time-stamping feature    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;    ECanaShadow.CANMC.bit.SCB = 1;    ECanaShadow.CANMC.bit.ABO = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;    ECanaRegs.CANME.all = 0x0L;
    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,    // all bits (including reserved bits) of MSGCTRL must be initialized to zero    pMbox = &ECanaMboxes.MBOX0;    pLam  = &ECanaLAMRegs.LAM0;
    for(x=0;x<32;x++)    {
        pMbox[x].MSGID.all    = 0x040000000L;        pMbox[x].MSGCTRL.all  = 0x000000000L;        pMbox[x].MDL.all      = 0x000000000L;
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        pMbox[x].MDH.all      = 0x000000000L;        pLam[x].all           = 0x0FFFFFFFFL;    }
    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again    // as a matter of precaution.  
    ECanaRegs.CANTA.all= 0xFFFFFFFF;/* Clear all TAn bits */
     ECanaRegs.CANRMP.all = 0xFFFFFFFF;/* Clear all RMPn bits */
     ECanaRegs.CANGIF0.all = 0xFFFFFFFF;/* Clear all interrupt flag bits */    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
    /* Configure bit timing parameters for eCANA*/    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1             // Set CCR = 1    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    do    {
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;
     } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..    ECanaShadow.CANBTC.all = 0;
    /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).     Bit rate = 500 kbps,TQ = 1/CANCLK*(BRPreg + 1),CANCLK=SYSCLKOUT/2,    Bit-time = ((TSEG1reg + 1) + (TSEG2reg + 1) + 1)*TQ, */    ECanaShadow.CANBTC.bit.BRPREG = 9;    ECanaShadow.CANBTC.bit.TSEG2REG = 1;    ECanaShadow.CANBTC.bit.TSEG1REG = 6;
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0             // Set CCR = 0    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    do    {
       ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be  cleared..
    ECanaRegs.CANMIL.all = 0x000000000L;     // The mailbox interrupt is generated on interrupt line 0    ECanaRegs.CANMIM.all = 0x0FFFFFFFFL;     // Mailbox 0~31 interrupt is enabled.    ECanaRegs.CANGIM.all = 0x000007F01L;     // I1EN interrupt disable                                             // MTOM and TCOIM disable                                      // AAIM,WDIM,WUIM,RMLIM,BOIM,EPIM,I0EN and WLIM interrupt enable                        // All global interrupts are mapped to the ECAN0INT     ECanaRegs.CANGIF0.all= 0x00003FF00L;     // Clear Global Interrupt Flag 0
    ECanaRegs.CANMD.all  = 0x00000ffffL;     // mbox0~15 reciever,mailbox16~31 transmiter    ECanaRegs.CANOPC.all = 0x00000ffffL;     // Overwrite Protection for mbox0~15    ECanaRegs.CANME.all  = 0x00000ffffL;     // enble all mailboxs for tx or rx    EDIS;}

这是两个不同的CAN口。

对的 两路CAN