KeyStone 的DDR3设计要求

2019-07-29 16:21发布

KeyStone 的DDR3设计要求
This document provides implementationinstructions for the DDR3 interface incorporated in the Texas Instruments (TI)Keystone series of DSP devices. It supports 1333 MT/s and higher memory speedsin a variety of topologies (see to the Data Manual for supported speeds). Thisdocument assumes the user has a familiarization with DRAM implementationconcepts and constraints. When searching for a particular configuration see theappendix, which will alleviate the need for searching the entire document whichcontains all possible variations.
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zhangmangui
1楼-- · 2019-07-29 20:22
欢迎分享
muzi820305
2楼-- · 2019-07-29 23:21
谢谢分享
long009
3楼-- · 2019-07-30 03:10
:handshake

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