你好,对呀,这个理论上是这样,但是却差得远,现在是ARM在SCK下降沿开始发送数据,FPGA在上升沿进行数据采样,不应该有问题呀,正好把数据采集过来,你看下代码,希望能给出建议
//同步寄存器,消除亚稳态
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
s0 <= 1'b0;
s1 <= 1'b0;
end
else begin
s0 <= SCK;
s1 <= s0;
end
//数据寄存器
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
t0 <= 1'b0;
t1 <= 1'b0;
end
else begin
t0 <= s1;
t1 <= t0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
sck_r0 <= 1'b0; //sck of the idle state is high
sck_r1 <= 1'b0;
end
else
begin
sck_r0 <= t1;
sck_r1 <= sck_r0;
end
end
assign sck_n = (!sck_r0 & sck_r1); //capture the sck negedge
assign sck_p = (sck_r0 & !sck_r1); //capture the sck posedge
//-----------------------spi_slaver read data-------------------------------
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rxd_data <= 1'b0;
rxd_flag_r <= 1'b0;
rxd_state <= 1'b0;
end
else if(sck_p && !CS_N)
begin
case(rxd_state)
4'd0:begin
rxd_data[7] <= MOSI;
rxd_flag_r <= 1'b0; //reset rxd_flag
rxd_state <= 4'd1;
end
4'd1:begin
rxd_data[6] <= MOSI;
rxd_state <= 4'd2;
end
4'd2:begin
rxd_data[5] <= MOSI;
rxd_state <= 4'd3;
end
4'd3:begin
rxd_data[4] <= MOSI;
rxd_state <= 4'd4;
end
4'd4:begin
rxd_data[3] <= MOSI;
rxd_state <= 4'd5;
end
4'd5:begin
rxd_data[2] <= MOSI;
rxd_state <= 4'd6;
end
4'd6:begin
rxd_data[1] <= MOSI;
rxd_state <= 4'd7;
end
4'd7:begin
rxd_data[0] <= MOSI;
rxd_flag_r <= 1'b1; //reset rxd_flag
rxd_state <= 4'd0;
end
default: ;
endcase
end
end
你好,对呀,这个理论上是这样,但是却差得远,现在是ARM在SCK下降沿开始发送数据,FPGA在上升沿进行数据采样,不应该有问题呀,正好把数据采集过来,你看下代码,希望能给出建议
//同步寄存器,消除亚稳态
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
s0 <= 1'b0;
s1 <= 1'b0;
end
else begin
s0 <= SCK;
s1 <= s0;
end
//数据寄存器
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
t0 <= 1'b0;
t1 <= 1'b0;
end
else begin
t0 <= s1;
t1 <= t0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
sck_r0 <= 1'b0; //sck of the idle state is high
sck_r1 <= 1'b0;
end
else
begin
sck_r0 <= t1;
sck_r1 <= sck_r0;
end
end
assign sck_n = (!sck_r0 & sck_r1); //capture the sck negedge
assign sck_p = (sck_r0 & !sck_r1); //capture the sck posedge
//-----------------------spi_slaver read data-------------------------------
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rxd_data <= 1'b0;
rxd_flag_r <= 1'b0;
rxd_state <= 1'b0;
end
else if(sck_p && !CS_N)
begin
case(rxd_state)
4'd0:begin
rxd_data[7] <= MOSI;
rxd_flag_r <= 1'b0; //reset rxd_flag
rxd_state <= 4'd1;
end
4'd1:begin
rxd_data[6] <= MOSI;
rxd_state <= 4'd2;
end
4'd2:begin
rxd_data[5] <= MOSI;
rxd_state <= 4'd3;
end
4'd3:begin
rxd_data[4] <= MOSI;
rxd_state <= 4'd4;
end
4'd4:begin
rxd_data[3] <= MOSI;
rxd_state <= 4'd5;
end
4'd5:begin
rxd_data[2] <= MOSI;
rxd_state <= 4'd6;
end
4'd6:begin
rxd_data[1] <= MOSI;
rxd_state <= 4'd7;
end
4'd7:begin
rxd_data[0] <= MOSI;
rxd_flag_r <= 1'b1; //reset rxd_flag
rxd_state <= 4'd0;
end
default: ;
endcase
end
end
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