是带7位数码管的模100计数器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
       port(clk,rst:in std_logic;
                      digit1,digit2:out std_logic_vector(6 downto 0));
end top;

architecture Behavioral of top is
begin
     process(clk,rst)
           variable temp1,temp2:integer range 0 to 10;
          begin
     if(rst='1')then
          temp1:=0;
          temp2:=0;
     elsif(clk'event and clk='1')then
          temp1:=temp1+1;
          if(temp1=10)then
          temp1:=0;
          temp2:=temp2+1;
          if(temp2=10)then
          temp2:=0;
     end if;
          end if;
          end if;

   case temp1 is
        when 0 => digit1 <= "1111110";
        when 1 => digit1 <= "0110000";
        when 2 => digit1 <= "1101101";
        when 3 => digit1 <= "1111001";
        when 4 => digit1 <= "0110011";
        when 5 => digit1 <= "1011011";
        when 6 => digit1 <= "1011111";
        when 7 => digit1 <= "1110000";
        when 8 => digit1 <= "1111111";
        when 9 => digit1 <= "1111011";
        when others => null;
        end case;
       
        case temp2 is
        when 0 => digit2 <= "1111110";
        when 1 => digit2 <= "0110000";
        when 2 => digit2 <= "1101101";
        when 3 => digit2 <= "1111001";
        when 4 => digit2 <= "0110011";
        when 5 => digit2 <= "1011011";
        when 6 => digit2 <= "1011111";
        when 7 => digit2 <= "1110000";
        when 8 => digit2 <= "1111111";
        when 9 => digit2 <= "1111011";
        when others => null;
        end case;
end process;
end Behavioral;
总是有如下的警告
WARNING:HDLCompiler:1369 - "C:Userszmcounter op.vhd" Line 11: Possible infinite loop; process does not have a wait statement
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit1<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <digit2<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.


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