[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I3, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/maintenance_request.maint_sre_r_lcl_i_1.
[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/maintenance_request.maint_srx_r_lcl_i_1.
[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/i___82.
[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/i___83.
[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_mig/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/i___81_i_2.
由以上可见，它指向的都是我生成的mig的IP核的底层文件，我找了好久都找不到这个引脚在哪儿？请问大大们，这个问题是因为引脚没连导致的吗？如何解决？
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小平头技术问答
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
port (
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
clk_i : in std_logic;
reset : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
component mig_7series_0
port(
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(28 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(255 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(31 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(255 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
-- Reference Clock Ports
clk_ref_i : in std_logic;
device_temp_o : out std_logic_vector(11 downto 0);
sys_rst : in std_logic
);
end component mig_7series_0;
component MIG_CTRL is
Port (
app_addr : out std_logic_vector(28 downto 0);
app_cmd : out std_logic_vector(2 downto 0);
app_en : out std_logic;
app_wdf_data : out std_logic_vector(255 downto 0);
app_wdf_end : out std_logic;
app_wdf_mask : out std_logic_vector(31 downto 0);
app_wdf_wren : out std_logic;
app_rd_data : in std_logic_vector(255 downto 0);
app_rd_data_end : in std_logic;
app_rd_data_valid : in std_logic;
app_rdy : in std_logic;
app_wdf_rdy : in std_logic;
ui_clk : in std_logic;
ui_clk_sync_rst : in std_logic;
init_calib_complete : in std_logic
);
end component MIG_CTRL;
component clk_wiz_0
port(
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
-- Clock in ports
clk_in1 : in std_logic
);
end component;
signal app_addr : std_logic_vector(28 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector(255 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(31 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector(255 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal app_sr_req : std_logic;
signal app_ref_req : std_logic;
signal app_zq_req : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal init_calib_complete : std_logic;
signal ui_clk : std_logic;
signal ui_clk_sync_rst : std_logic;
signal sys_clk_i : std_logic;
signal clk_ref_i : std_logic;
signal sys_rst : std_logic;
begin
clk_wiz_0_inst : clk_wiz_0
port map(
-- Clock out ports
clk_out1 => sys_clk_i,
clk_out2 => clk_ref_i,
-- Status and control signals
reset => reset,
locked => sys_rst,
-- Clock in ports
clk_in1=> clk_i
);
u_mig : mig_7series_0
port map (
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => init_calib_complete,
device_temp_o => open,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_ref_req => app_ref_req,
app_zq_req => app_zq_req,
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
-- Reference Clock Ports
clk_ref_i => clk_ref_i,
sys_rst => sys_rst
);
U_MIG_CTRL : MIG_CTRL Port map(
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
app_wdf_mask => app_wdf_mask,
init_calib_complete => init_calib_complete
);
end architecture arch_example_top;
这是我的顶层文件，不知道是语法的问题还是逻辑的问题，我是把DDR3的硬件引脚拉出来放在了顶层里，用户引脚和控制文件相连，调用了一个CLK wiz，拉出来两根输入线一个reset，一个clk_i，也放在了顶层端口里。 但是实现的时候总是会报错，IP核我是直接声明例化的，也没有改动，ddr3引脚是直接在IP核配置的时候填进去的，我也排查了引脚，没有发现有遗漏啊。
解决了，在Vivado的实现里有个DRC report,里面会告诉哪些地方没连，其实有三个用户请求引脚我映射出来了，官方例子里面是把这三个引脚直接映射成低电平，即‘0‘
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