用modelsim
仿真verilog时,建2个.v文件
n
and_2.v和test_
for_nand.v,编译通过,对
test_for_nand.v仿真时,报错:
# ** Error: F:/Modelsim/Nand/test_for_nand.v(16): Missing instance name in instantiation of 'nand_2'.
# Optimization failed
# Error loading design
请教什么原因啊?
nand_2.v
module nand_2(in1,in2,out);
input in1,in2;
output out;
assign out=~(in1&in2);
endmodule
test_for_nand.v
`timescale 10ns/1ns
`include "nand_2.v"
module test_for_nand2;
reg a,b;
wire out0;
initial
begin
a=0;b=0;
#1 a=1;b=0;
#1 a=0;b=1;
#1 a=1;b=1;
end
initial
begin
$monitor("Time=%0d a=%b b=%b out=%b",$time,a,b,out0);
end
nand_2(a,b,out0);
endmodule
此帖出自
小平头技术问答
test 仿真程序没有映射 源程序端口!
请参考一个实际仿真程序例子!
请问如何解决?
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