江湖救急！VIVADO错误 小白求帮助

2019-03-25 07:26发布

站内问答 / FPGA
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我是个小白   从网上找的vivado源程序  没有检出错误  但是仿真和综合的时候显示有错误  
综合的时候只显示有错误  但是我没找到怎么看
仿真的时候 显示的错误如图
他让我看xvlog  我也看不懂  具体如下：
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/src/bd/hdmi_in/ipshared/9097/src/mmcme2_drp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mmcme2_drp
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_processing_system7_0_0/sim/hdmi_in_processing_system7_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_processing_system7_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_v_axi4s_vid_out_0_0/sim/hdmi_in_v_axi4s_vid_out_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_v_axi4s_vid_out_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_v_vid_in_axi4s_0_0/sim/hdmi_in_v_vid_in_axi4s_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_v_vid_in_axi4s_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_xbar_0/sim/hdmi_in_xbar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_xbar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_xbar_1/sim/hdmi_in_xbar_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_xbar_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_s00_regslice_0/sim/hdmi_in_s00_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_s00_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_s01_regslice_0/sim/hdmi_in_s01_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_s01_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_m00_data_fifo_0/sim/hdmi_in_m00_data_fifo_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_m00_data_fifo_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_m00_regslice_0/sim/hdmi_in_m00_regslice_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_m00_regslice_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_pc_0/sim/hdmi_in_auto_pc_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_pc_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_us_df_0/sim/hdmi_in_auto_us_df_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_us_df_0
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_us_df_1/sim/hdmi_in_auto_us_df_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_us_df_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.ip_user_files/bd/hdmi_in/ip/hdmi_in_auto_pc_1/sim/hdmi_in_auto_pc_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hdmi_in_auto_pc_1
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/Zybo-hdmi-in-master/proj/hdmi-in.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl

求大神帮我看看
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11条回答
lll424168013
1楼-- · 2019-03-26 08:38
不足论 发表于 2017-5-23 11:04
轮流编译，定位问题原因

请问是轮流一个模块一个模块的仿真吗？  请问具体怎么去做呢？小白求解
不足论
2楼-- · 2019-03-26 12:37
lll424168013 发表于 2017-5-23 18:01
请问是轮流一个模块一个模块的仿真吗？  请问具体怎么去做呢？小白求解

轮流设置top去编译
lll424168013
3楼-- · 2019-03-26 17:24
不足论 发表于 2017-5-26 08:55
轮流设置top去编译

大神  我轮流去仿真的时候问题就出在这段程序上   但是看不懂  求帮看看
architecture STRUCTURE of hdmi_in_proc_sys_reset_0_0 is
  attribute C_AUX_RESET_HIGH : string;
  attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
  attribute C_AUX_RST_WIDTH : integer;
  attribute C_AUX_RST_WIDTH of U0 : label is 4;
  attribute C_EXT_RESET_HIGH : string;
  attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
  attribute C_EXT_RST_WIDTH : integer;
  attribute C_EXT_RST_WIDTH of U0 : label is 4;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynq";
  attribute C_NUM_BUS_RST : integer;
  attribute C_NUM_BUS_RST of U0 : label is 1;
  attribute C_NUM_INTERCONNECT_ARESETN : integer;
  attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
  attribute C_NUM_PERP_ARESETN : integer;
  attribute C_NUM_PERP_ARESETN of U0 : label is 1;
  attribute C_NUM_PERP_RST : integer;
  attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.hdmi_in_proc_sys_reset_0_0_proc_sys_reset
     port map (
      aux_reset_in => aux_reset_in,
      bus_struct_reset(0) => bus_struct_reset(0),
      dcm_locked => dcm_locked,
      ext_reset_in => ext_reset_in,
      interconnect_aresetn(0) => interconnect_aresetn(0),
      mb_debug_sys_rst => mb_debug_sys_rst,
      mb_reset => mb_reset,
      peripheral_aresetn(0) => peripheral_aresetn(0),
      peripheral_reset(0) => peripheral_reset(0),
      slowest_sync_clk => slowest_sync_clk
    );
end STRUCTURE;




错误提示： 'compile' step failed with error(s). Please check the Tcl console output or 'E:/HDMItest/T1/t1/t1.sim/sim_1/behav/xvhdl.log' file for more information.
不足论
4楼-- · 2019-03-26 19:33
lll424168013 发表于 2017-5-26 15:11
大神  我轮流去仿真的时候问题就出在这段程序上   但是看不懂  求帮看看
architecture STRUCTURE of hdm ...

私聊
jxl_annie0219
5楼-- · 2019-03-26 23:08
再生成block design时检查了吗？
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