If you notice no DCLK or DATA output from the configuration device, it is possible
the configuration device is in a slave mode or idle state. When using a
configuration device, the FPGA’s VCCINT supply must be powered up before the
configuration device exits POR. If the configuration device exits POR before the
FPGA is powered up, the configuration device will enter slave mode (EPC2/EPC1
device) or will enter an idle state (enhanced configuration device).
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https://www.altera.co.jp/ja_JP/p ... g/cfg_ch11_vol2.pdf
If you notice no DCLK or DATA output from the configuration device, it is possible
the configuration device is in a slave mode or idle state. When using a
configuration device, the FPGA’s VCCINT supply must be powered up before the
configuration device exits POR. If the configuration device exits POR before the
FPGA is powered up, the configuration device will enter slave mode (EPC2/EPC1
device) or will enter an idle state (enhanced configuration device).
晶振呢？看看低温下晶振正常吗？
这个也测试过的，加电延迟200ms，PORSEL置低
晶振没问题啊，但是这个有什么联系吗？
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