我是用XILINX XC9500XL-144芯片，配置引脚p30为时钟输入，综合的时候出现
waring：Cpld - Inferring BUFG constraint for signal 'iGCK1' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.

附源程序和ucf程序。
module re(iGCK1,ireset,oEnRESET,ostart);
input iGCK1;
input ireset;
output oEnRESET;

output ostart;
reg [18:0]ob;

reg oreset,o1start;
                        
always@(posedge iGCK1)        
begin
if(ireset)
begin        
oreset<=1;
ob<=0;
o1start<=0;
end
else if(!ireset)
begin
if(ob<=350110)
  ob<=ob+1;
else
ob<=ob;
end
case (ob)
  10:oreset<=0;
  110:oreset<=1;
  350110:o1start<=1;
endcase  
end
                                          
assign oEnRESET=oreset;
assign ostart=o1start;

endmodule

ucf程序：
NET"iGCK1" LOC="p30";
NET"ireset" LOC="p132";
NET"oEnRESET" LOC="p85";
NET"ostart" LOC="p79";

此帖出自小平头技术问答