VHDL 模块:
ENTITY SIN IS
PORT (CLK,kd,ku: IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ;
daclk,LED: OUT STD_LOGIC
);
END;
Verilog调用示例:
SIN u0
(
.CLK (clk ), // I, 1-bit, system clock, 50 MHz
.kd (kd ), // I, 1-bit, frequency decrease
.ku (ku ), // I, 1-bit, frequency increase
.DOUT ( ), // O, 8-bit,
.daclk ( ), // O, 1-bit,
.LED ( ) // O, 1-bit, led
);
ENTITY SIN IS
PORT (CLK,kd,ku: IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ;
daclk,LED: OUT STD_LOGIC
);
END;
Verilog调用示例:
SIN u0
(
.CLK (clk ), // I, 1-bit, system clock, 50 MHz
.kd (kd ), // I, 1-bit, frequency decrease
.ku (ku ), // I, 1-bit, frequency increase
.DOUT ( ), // O, 8-bit,
.daclk ( ), // O, 1-bit,
.LED ( ) // O, 1-bit, led
);
在Veril0g工程中,然后在Veril0g语中直接
调用
在Veril0g工程中,然后在Veril0g语中直接
调用
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