小弟正在做基于FPGA的视频监控设计中 遇到了VGA程序出现BUG问题，有哪位大神能解？跪求

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VGA is
generic(H_VIDEO:integer:=800;
  H_SYNCTIME :integer:=120;
  H_BACK : integer:=21;
  H_FRONT :integer:=53;
  V_VIDEO :integer:=600;
  H_SYNCTIME :integer:=8;
  H_BACK :integer:=24;
  H_FRONT :integer:=30;
  H_PERIOD = H_BACK + HVIDEO + H_FRONT + H_SYNCTIME;
  V_PERIOD = V_BACK + VVIDEO + V_FRONT + V_SYNCTIME;);
architecture rtl of VGA is
signal x_cnt,y_cnt:std_logic_vector(10 downto 0);
--begin
process(clk,reset)
  begin
  if(reset='0') then
   x_cnt<="00000000000";
  elsif(clk 'event and clk =1) then
   if(x_cnt =H_PEIROD)
    x_cnt<="00000000000";
   else
    x_cnt<= x_cnt +1;
   end if;
  end if;
end process;
process(clk,reset)
  begin
  if(reset='0') then
   y_cnt<="0000000000";
  elsif(clk 'event and clk ='1') then
   if(y_cnt =V_PEIROD)
    y_cnt<="0000000000";
   else
    y_cnt<= y_cnt +1;
   end if;
  end if;
end process;
process(clk,reset)
begin
  if(reset ='0') then
  hsync<='1';
elsif(clk 'event and clk ='1') then
  if(x_cnt >= H_VIDEO +H_FRONT )&(x_xnt <=H_VIDEO +H_FRONT +H_SYNCTIME)
   hsync<='0';
  else
   hsync <= '1';
  end if;
end if;
end process;
process(clk,reset)
begin
  if(reset ='0') then
  vsync<='1';
elsif(clk 'event and clk ='1') then
  if(y_cnt >= H_VIDEO + H_FRONT )&(y_xnt <=V_VIDEO +V_FRONT +V_SYNCTIME)
   hsync<= '0';
  else
   hsync<= '1';
  end if;
end if;
end process;
end rtl; 此帖出自小平头技术问答