请教高手:用quartus仿真了个7段led译码器,功能仿真输出正常,但时序仿真输出有很多毛刺,还没找到解决的方法,望高手给点建议,谢谢!
--------------------------------------------------------------------
--Led七段译码器
--共阴
--date:2012.09.27
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led_7bitdecoder is
port(datain : in std_logic_vector(03 downto 0);
en : in std_logic;
dataout: out std_logic_vector(06 downto 0));
end led_7bitdecoder;
architecture Led_7bit_Decoder of led_7bitdecoder is
signal reg_7 : std_logic_vector(06 downto 0);
begin
process(en,datain,reg_7)
begin
if en='1' then
case datain is
when "0000" => reg_7<="1000000" ; --0
when "0001" => reg_7<="1111001" ; --1
when "0010" => reg_7<="0100100" ; --2
when "0011" => reg_7<="0110000" ; --3
when "0100" => reg_7<="0011001" ; --4
when "0101" => reg_7<="0010010" ; --5
when "0110" => reg_7<="0000011" ; --6
when "0111" => reg_7<="1111000" ; --7
when "1000" => reg_7<="0000000" ; --8
when "1001" => reg_7<="0011000" ; --9
when "1010" => reg_7<="0001000" ; --A
when "1011" => reg_7<="0000011" ; --B
when "1100" => reg_7<="0100111" ; --C
when "1101" => reg_7<="0100001" ; --D
when "1110" => reg_7<="0000110" ; --E
when "1111" => reg_7<="0001110" ; --F
when others => null;
end case;
dataout<=reg_7;
end if;
end process;
--dataout<=reg_7;
end Led_7bit_Decoder;
[
本帖最后由 ksqnhm 于 2012-9-27 13:49 编辑 ]
此帖出自
小平头技术问答
1是重新编码,解决竞争与冒险出现的毛刺
2是采用时钟采样
3就是直接用7段码显示译码芯片咯,当然这个就跟VHDL就没关系啦
4还有可以根据毛刺大小和你刷新频率给电路加滤波,呵呵
一周热门 更多>