刚刚开始用Verilog编写东西，出现如下问题，求解。代码如下：

module mux(select_0,a,b,select,outa1,outb1,outa2,outb2,outa3,outb3,outa4,outb4,outa5,outb5,outa6,outb6,outa7,outb7,outa8,outb8);
input [8:1] a,b;
input [3:1] select;
input select_0;
output [8:1] outa1,outb1,outa2,outb2,outa3,outb3,outa4,outb4,outa5,outb5,outa6,outb6,outa7,outb7,outa8,outb8;
reg [8:1] outa1,outb1,outa2,outb2,outa3,outb3,outa4,outb4,outa5,outb5,outa6,outb6,outa7,outb7,outa8,outb8;
always @ (a or b or select or select_0)
begin
if(select_0)
begin
  case(select)
   3'b000:outa1=a,outb1<=b;
   3'b001:outa2=a;outb2=b;
   3'b010:outa3=a,outb3=b;
   3'b011:outa4=a,outb4=b;
   3'b100:outa5=a,outb5=b;
   3'b101:outa6=a,outb6=b;
   3'b110:outa7=a,outb7=b;
   3'b111:outa8=a,outb8=b;
   default:null;
  endcase
end
end
endmodule


报错如下：
Error (10170): Verilog HDL syntax error at mux.v(14) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(15) near text "="
Error (10170): Verilog HDL syntax error at mux.v(16) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(17) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(18) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(19) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(20) near text ",";  expecting ";"
Error (10170): Verilog HDL syntax error at mux.v(21) near text ",";  expecting ";"
Error (10112): Ignored design unit "mux" at mux.v(1) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 0 warnings
Error: Peak virtual memory: 164 megabytes
Error: Processing ended: Sun Oct 28 10:52:47 2012
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 0 warnings 此帖出自小平头技术问答