LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY USB_FPGA IS
GENERIC (
FIFOLENTH : integer := 1024; --FIFO长度2048
FIFOWITH : integer := 16; --FIFO宽度------------8----16---
PACKAGENUM : integer := 256 --FIFO单个数据包长度--512--256--
);
PORT
(
IFCLK : IN STD_LOGIC ;
RESETFPGA : IN STD_LOGIC ;
-- FX2 SLAVE FIFO
FX2FD : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ;
CTL0_FLAGA : IN STD_LOGIC ;
CTL1_FLAGB : IN STD_LOGIC ;
CTL2_FLAGC : IN STD_LOGIC ;
RDY0_SLRD : OUT STD_LOGIC ;
RDY1_SLWR : OUT STD_LOGIC ;
PA7_FLAGD : IN STD_LOGIC ;
PA6_PKTEND : OUT STD_LOGIC ;
PA5_FIFOADR1 : OUT STD_LOGIC ;
PA4_FIFOADR0 : OUT STD_LOGIC ;
PA2_SLOE : OUT STD_LOGIC ;
PA0_INT0 : IN STD_LOGIC ;
PA1_INT1 : IN STD_LOGIC ;
LED1 : OUT STD_LOGIC
);
END USB_FPGA;
ARCHITECTURE ARC_USB_FPGA OF USB_FPGA IS
--FIFO
TYPE fifo_arry IS ARRAY(0 to (FIFOLENTH-1)) OF bit_vector((FIFOWITH-1) DOWNTO 0);
SIGNAL fifomemory:fifo_arry;
SIGNAL fifowraddr,fifordaddr : NATURAL RANGE 0 TO (FIFOLENTH-1) ;
SIGNAL data2usb,data2fpga : STD_LOGIC_VECTOR((FIFOWITH-1) DOWNTO 0) ;
SIGNAL wrstate : NATURAL RANGE 0 TO PACKAGENUM ;
SIGNAL fifoadrcs : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SIGNAL slrdbuf,slwrbuf,sloebuf : STD_LOGIC ;
SIGNAL led1buf : STD_LOGIC ;
BEGIN
LED1 <= led1buf;
PA5_FIFOADR1 <= PA1_INT1;
PA4_FIFOADR0 <= PA0_INT0;
fifoadrcs <= PA1_INT1 & PA0_INT0;
PA2_SLOE <= sloebuf;
RDY0_SLRD <= slrdbuf ;
RDY1_SLWR <= slwrbuf ;
PA6_PKTEND <= '1';
PROCESS(PA1_INT1)
BEGIN
IF(RESETFPGA = '0') THEN
data2fpga <= FX2FD;
FX2FD <="ZZZZZZZZZZZZZZZZ" ;
ELSIF(PA1_INT1='0') THEN
data2fpga <= FX2FD;
FX2FD <="ZZZZZZZZZZZZZZZZ" ;
ELSE
data2fpga <= "ZZZZZZZZZZZZZZZZ" ;
FX2FD <=data2usb ;
END IF;
END PROCESS;
PROCESS(RESETFPGA,IFCLK)
BEGIN
IF(RESETFPGA = '0') THEN
led1buf <= '1';
sloebuf <= '1';
slrdbuf <= '1';
slwrbuf <= '1';
fifowraddr <= 0;
fifordaddr <= 0;
ELSIF(IFCLK'event AND IFCLK='1') THEN
IF(PA1_INT1='0') THEN
led1buf <= '0';
sloebuf <= '0';
slwrbuf <= '1';
IF(CTL0_FLAGA = '1') THEN --wr to fpga
CASE wrstate IS
WHEN 0 =>
wrstate <= wrstate + 1;
slrdbuf <= '0';
WHEN PACKAGENUM =>
wrstate <= 0 ;
slrdbuf <= '1';
fifomemory(fifowraddr) <= to_bitvector(data2fpga);
IF (fifowraddr>=fifowraddr'high) THEN
fifowraddr<=0;
ELSE
fifowraddr<=fifowraddr+1;
END IF;
WHEN OTHERS =>
wrstate <= wrstate + 1;
slrdbuf <= '0';
fifomemory(fifowraddr) <= to_bitvector(data2fpga);
IF (fifowraddr>=fifowraddr'high) THEN
fifowraddr<=0;
ELSE
fifowraddr<=fifowraddr+1;
END IF;
END CASE;
IF((fifowraddr=511) AND (data2fpga="1111111111111110")) THEN
led1buf <= '0';
ELSIF(fifowraddr=(FIFOLENTH-1)) THEN
led1buf <= '1';
END IF;
ELSE
slrdbuf <= '1';
END IF;
ELSE
led1buf <= '1';
sloebuf <= '1';
slrdbuf <= '1';
IF((CTL2_FLAGC = '1') AND (fifowraddr /= fifordaddr)) THEN --rd from fpga
slwrbuf <= '0';
data2usb <= to_stdlogicvector(fifomemory(fifordaddr));
IF(fifordaddr>=fifordaddr'high) THEN
fifordaddr<=0;
ELSE
fifordaddr<=fifordaddr+1;
END IF;
IF(fifordaddr=511) THEN
led1buf <= '0';
ELSIF(fifordaddr=(FIFOLENTH-1)) THEN
led1buf <= '1';
END IF;
ELSE
slwrbuf <= '1';
data2usb <= "ZZZZZZZZZZZZZZZZ";
END IF;
END IF;
END IF;
END PROCESS;
END ARC_USB_FPGA;
希望有大神帮我写一个verilog的程序,要求是有点过分,但是确实是自己没什么办法。恳请帮我一下,谢谢了。。。。。
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