module ff(rw,oer,ce,lclk,busyr,lint_r,led,lblast,lserr,lads,lholda,lhold,la,lreseto,lwait,lready,lwr,lint,cs);
input lads; //address strobe form 9054
input lhold; //bus hold request from 9054
input lblast; //burst last from 9054
input lreseto;
input lwr;
input lint;
input [3:0]la;
input busyr;
input lserr;
input lwait;
input lclk;
output cs;
output lready;
output rw;
output oer;
output ce;
output [3:0]led;
output lholda;
output lint_r;
reg lholda;
reg [3:0]led;
wire cs;
reg ce;
reg oer;
reg lint_r;
reg [3:0]state,next_state;
reg counter_ena;
wire counter_ovf;
reg counter_clear;
reg [3:0]counter;
// wire lholda;
reg lready;
reg rw;
//parameter X =4'b1010;
parameter IDLE =4'b0000,
RD_WR =4'b0001,
READ1 =4'b0010,
READ2 =4'b0011,
READ3 =4'b0100,
READ4 =4'b0101,
WRITE1 =4'b0110,
WRITE2 =4'b0111,
WRITE3 =4'b1000,
WRITE4 =4'b1001;
assign cs=(la==4'b1010)?0:1;
// assign lholda=(lhold==1&&busyr==1&&cs==1)?1:0;
/*always@(posedge lclk or negedge lreseto)
if(!lreseto)
state<=IDLE;
else
state<=next_state;
always@(state)
begin
next_state=4'b0000;
case(state)
IDLE:if(lhold&&busyr)
next_state=RD_WR;
else
next_state=IDLE;
RD_WR:if(lwr==1)
next_state=WRITE1;
else
next_state=READ1;
WRITE1:if(!lads)
next_state=WRITE2;
else
next_state=WRITE1;
WRITE2:
next_state=WRITE3;
WRITE3:if(!lblast)
next_state=WRITE4;
else
next_state=WRITE1;
WRITE4:if(!lhold)
next_state=IDLE;
else
next_state=WRITE4;
READ1:if(!lads)
next_state=READ2;
else
next_state=READ1;
READ2:next_state=READ3;
READ3:if(!lblast)
next_state=READ4;
else
next_state=READ1;
READ4:if(!lhold)
next_state=IDLE;
else
next_state=READ4;
endcase
end
*/
always @(posedge lclk or negedge lreseto)
begin
if(!lreseto)
begin
state <=IDLE;
lholda<=0;
ce<=1;
led[3:0]<=4'b0000;
end
else
begin
case(state)
IDLE: begin
led[3:0]<=4'b0001;
if(cs==0&&lhold==1&&busyr==1)
state<=RD_WR;
else
state<=IDLE;
lint_r<=1;
end
RD_WR:begin
led[3:0]<=4'b0010;
lholda<=1;
if(lwr==1)
state<=WRITE1;
else
state<=READ1;
end
READ1:begin
led[3:0]<=4'b0011;
rw<=0;
ce<=1;
if(lads==0)
state<=READ2;
else
state<=READ1;
end
READ2:begin
led[3:0]=4'b0100;
lready<=0;
rw<=1;
state<=READ3;
end
READ3:begin
led[3:0]<=4'b0101;
ce<=0;
oer<=0;
if(lblast==0)
state<=READ3;
else
state<=READ1;
end
READ4:begin
led[3:0]<=4'b0110;
lready<=1;
ce<=1;
if(lhold==0)
state<=IDLE;
else
state<=READ4;
end
WRITE1:begin
led[3:0]<=4'b1000;
rw<=1;
ce<=1;
if(lads==0)
state<=WRITE2;
else
state<=WRITE1;
end
WRITE2:begin
led[3:0]<=4'b1001;
lready<=0;
rw<=0;
state<=WRITE3;
end
WRITE3:begin
led[3:0]<=4'b1010;
ce<=0;
if(lblast==0)
state<=WRITE4;
else
state<=WRITE1;
end
WRITE4:begin
led[3:0]<=4'b1011;
lready<=1;
ce<=1;
rw<=1;
if(lhold==0)
state<=IDLE;
else
state<=WRITE4;
end
default state<=IDLE;
endcase
end
/*always @(posedge lclk or negedge lreseto)
begin
if(lreseto==0)
counter[3:0]=4'b0000;
else if(counter_ena==1)
counter[3:0]=counter+1;
else if(counter_clear==1)
counter[3:0]=4'b0000;
end
assign counter_ovf=(counter[3:0]==4'b1000);*/
end
endmodule
测试文件
`timescale 1ns/1ns;
module pci_cpld_top;
reg lclk;
reg lhold;
reg lads;
reg lblast;
wire lready;
wire lint_r;
reg lwr;
wire lholda;
reg busyr;
reg [3:0]la;
reg lreseto;
wire [3:0]led;
initial
begin
lclk=0;
lhold=0;
lads=1;
lblast=1;
lwr=1;
busyr=1;
lreseto=1;
#10 lreseto=0;
#10 lreseto=1;
la[3:0]=4'b1010;
end
always
begin
#10 lhold=1;
#20 lads=0;
#21 lads=1;
#40 lblast=0;
#20 lblast=1;
#20 lhold=0;
#30 lhold=1;
#20 lads=0;
#20 lads=1;
#40 lblast=0;
#20 lblast=1;
#20 lhold=0;
end
always
begin
#10 lclk=~lclk;
end
initial
#10000 $finish;
ff m(.lreseto(lreseto),.led(led),.lint_r(lint_r),.cs(cs),.la(la),.oer(oer),.lholda(lholda),.rw(rw),.lhold(lhold),.lads(lads),.lblast(lblast),.lready(lready),.ce(ce),.lwr(lwr));
endmodule
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