以下的代码，老是通不过编译，显示的错误是：Error (10822): HDL error at test17.vhd(384): couldn't implement registers for assignments on this clock edge 这段代码的主要意思是当speed2有下降沿时，通过外部时钟开始计数，等到“11111111”时间后，如果speed2还是低电平，则给计数器result加1，否则不加。主要是防止信号误操作的。 请各位大侠帮忙看看，是顺序有问题，还是哪里 有问题。谢谢   test:process(speed2,EXTCLK)
 begin
 case speedtest3 is
when 0 =>
    if speed2'event and speed2='0'then
     m<='1';
     end if;
     when 1 =>
   result1<=result;
     result<="0000000000000000";
end case;
if(m<='1')then
  if EXTCLK'event and EXTCLK='1'then
     if counter100="11111111" then
        if(speed2<='0')then
        result<=result+1;
        counter100<="00000000";
        m<='0';
        else m<='0';
        counter100<="00000000";
        end if; 
      else
      counter100<=counter100+1;
     end if;
     end if;
     end if;
 end process; 此帖出自小平头技术问答