< / 原理图转换输出VHDL或VERILOG

喔，我自己写了一个
代码：----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:22:13 05/20/2012
-- Design Name:
-- Module Name:    some - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity some is
    Port ( A : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           C : out  STD_LOGIC;
           Z : out  STD_LOGIC);
end some;

architecture Behavioral of some is
signal s1:std_logic;
signal s2:std_logic;
signal s_z:std_logic;
signal s_c:std_logic;
begin
process(clk)is
begin
if(clk'event and clk='1')then
  s1<=a;
  end if;
   
end process;
s2<=s1 and a;
process
begin
  wait until clk'event and clk='1';
  s_c<=s2;
end process;
process
begin
  wait until clk'event and clk='1';
  s_z<=s1;
  end process;
  z<=s_z;
  c<=s_c;


end Behavioral;
实现了该电路图，但是我觉得太低效了。。自动转换会更高效吗？怎样自动转换，还望详细介绍。。

直接求出输出关于输入的逻辑表达方程，并采用卡诺图化简得最简式
在vhdl直接一句话实现，从而同时实现了硬件以及软件的高效运算。

怎样将原理图直接转换为VHDL语言，

quartus 中也有这个功能的，create  HDL file。。。