ERROR:HDLParsers:3375 - "D:/FPGA_code/p240_fir2/p240_fir2.vhd" Line 66. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2)

代码如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity p240_fir2 is
    GENERIC(n : integer := 4;
    m : integer := 4
);
Port ( x : in SIGNED(m-1 downto 0);
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        y : OUT SIGNED(2*m-1 DOWNTO 0));
end p240_fir2;

architecture Behavioral of p240_fir2 is
       TYPE registers IS ARRAY (n-2 DOWNTO 0) OF SIGNED(m-1 DOWNTO 0);
       TYPE coefficients IS ARRAY (n-1 DOWNTO 0) OF SIGNED(m-1 DOWNTO 0);
        SIGNAL reg : registers;
        CONSTANT coef : coefficients := ("0001","0010","0011","0100");
begin
        PROCESS(clk, rst)
        VARIABLE acc, prod : SIGNED(2*m-1 DOWNTO 0) := (OTHERS => '0');
        VARIABLE sign : STD_LOGIC;
BEGIN
        -----------------------RESET------------------------------
        IF(rst = '1') THEN
        FOR i IN n-2 DOWNTO 0 LOOP
            FOR j IN m-1 DOWNTO 0 LOOP
                reg(i)(j) <= '0';
            END LOOP;
        END LOOP;
         --------------register inference + MAC-------------------
        ELSIF(clk'EVENT AND clk = '1') THEN
            acc := coef(0)*x;
            FOR i IN 1 TO n-1 LOOP
                sign := acc(2*m-1);
                prod := coef(i)*reg(n-1-i);
                acc := acc + prod;
          -----------check overflow-----------------------
                IF((sign = prod(prod'left))AND(acc(acc'left) /= sign)) THEN
                    acc := (acc'LEFT => sign, OTHERS => (NOT sign));
                END IF;
           END LOOP;
           reg <= x&reg(n-2 DOWNTO 1);


        END IF;
        y <= acc;

END PROCESS;

end Behavioral; 此帖出自小平头技术问答