大家好，我是使用的STM32F103VET6，100pin情况下的FSMC，用来外接FPGA，现在的问题是当对FPGA写数据时，在NE1为低电平时，NADV和NWE信号翻转了好几次，我看手册NE1为低时，NADV不是就翻转一次，低电平时AD0-AD7上为地址，高电平时为数据吗？我这不管怎么设置，NADV都翻转好几次？下面是我的代码，使用库的形式，帮忙分析下到底是哪儿的错误呢？
void CPLD_Init(void) 
{  
  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure; 
  FSMC_NORSRAMTimingInitTypeDef  p; 
  GPIO_InitTypeDef GPIO_InitStructure;  
 
 /* Enable FSMC clocks */
 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); /*-- GPIO Configuration ------------------------------------------------------*/ 
  /* SRAM Data/address lines configuration */ 
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_14 | GPIO_Pin_15; 
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 
  GPIO_Init(GPIOD, &GPIO_InitStructure);  
   
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
  GPIO_Init(GPIOE, &GPIO_InitStructure); 
   
  /* NOE and NWE configuration */   
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; 
  GPIO_Init(GPIOD, &GPIO_InitStructure); 
 
  /*!< NE1 configuration */
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;  
  GPIO_Init(GPIOD, &GPIO_InitStructure); 
 
 /*NADV configuration */
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
  GPIO_Init(GPIOB, &GPIO_InitStructure);   /*!< Configure PD6 for NOR memory Ready/Busy signal */
//   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
//   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
//   GPIO_Init(GPIOD, &GPIO_InitStructure);   /*!< NBL0, NBL1 configuration ???©???????è??????×???????,????CPLD???è??*/ 
//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;   
//  GPIO_Init(GPIOE, &GPIO_InitStructure);   
   
/*-- FSMC Configuration ------------------------------------------------------*/ 
  p.FSMC_AddressSetupTime = 15; 
  p.FSMC_AddressHoldTime = 15;  //when mux, AddressHoldTime>=1
  p.FSMC_DataSetupTime = 15;    //DataSetupTime>=1
  p.FSMC_BusTurnAroundDuration = 15; 
  p.FSMC_CLKDivision = 0; 
  p.FSMC_DataLatency = 0; 
  p.FSMC_AccessMode = FSMC_AccessMode_B; 
 
  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1; 
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;  //mux mode
  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;  //set for get "NADV" signal
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; 
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; 
  //FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;   
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; 
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; 
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; 
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; 
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; 
  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
  /*!< Enable FSMC Bank1_SRAM Bank */ 
  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);    //  GPIOD->CRH &= 0x00ffffff;
//  GPIOD->CRH |= 0xbb000000;
//  
//  GPIOD->CRL &= 0x0f00ff00;
//  GPIOD->CRL |= 0xb0bb00bb;
//  
//  GPIOE->CRH &= 0xfffff000;
//  GPIOE->CRH |= 0x00000bbb;
//  
//  GPIOE->CRL &= 0x0fffffff;
//  GPIOE->CRL |= 0xb0000000;
//  
//  GPIOB->CRL &= 0x0fffffff;
//  GPIOB->CRL |= 0xb0000000;
  
//  FSMC_Bank1->BTCR[0] = 0x00000000;
//  FSMC_Bank1->BTCR[1] = 0x00000000;
//  //BCR
//  FSMC_Bank1->BTCR[0] |= 1<<12; //wr enable
//  FSMC_Bank1->BTCR[0] |= 1<<6;  //faccen
//  FSMC_Bank1->BTCR[0] |= 1<<3;  //memory typ
//  FSMC_Bank1->BTCR[0] |= 1<<1;  //mux
//  FSMC_Bank1->BTCR[0] |= 1<<0;  //mbken
//  FSMC_Bank1->BTCR[0] |= 1<<19;  
//  //BTR
//  FSMC_Bank1->BTCR[1] |= 15<<0;  //ADDSET
//  FSMC_Bank1->BTCR[1] |= 15<<4;  //addhold
//  FSMC_Bank1->BTCR[1] |= 15<<8;  //dataset
//  //FSMC_Bank1->BTCR[1] |= 1<<28;
 
} 

谢谢阿，寄存器操作我也试过，现象类似阿