module flash_mod(clk,rst,LED_OUT);
input clk;
inout rst;
output  LED_OUT;
//----------------------//
reg [19:0]cnt;
reg led_out;
parameter T50ms=20'd999_999;
//-------------------------//
//-------------------------//
always@(posedge clk,negedge rst)
  begin
  if(!rst)
  begin
   cnt<=0;
   led_out<='b0;end
   else if(cnt==T50ms)
        begin cnt<=0;
        led_out<=~led_out;end
        else cnt<=cnt+1;
        end
//---------------//

assign  LED_OUT=led_out;
endmodule
       
module run_mod (clk,rst,LED_OUT);
input rst;
input clk;
output [2:0]LED_OUT;
//-----------------------------//
reg [14:0]cnt0;
reg [6:0]cnt_100ms;
reg [2:0]led_out;
parameter T1ms=15'd19_999;
//----------------------------------//       

//--------------1ms计数器----------------//
always@(posedge clk, negedge rst)
begin
    if(!rst)
      begin
      
       cnt0<='b0;
                 cnt_100ms<=0; //------100ms计数器----------------------------//       
                 led_out<='b001;
       end
        //-------------每100ms移位一次-----------------//
          else if(cnt_100ms==7'd99)
         begin
                 if(led_out==3'b000)//判断是否移到末位//
                         led_out<=3'b001;
                      else led_out<={led_out[1:0],1'b0};
                   end
    else if (cnt0==T1ms)
                    begin
                        cnt0<='b0;
                        cnt_100ms<=cnt_100ms+1;
                        end
                  else cnt0<=cnt0+1;
               
end
          
       

assign LED_OUT=led_out;
endmodule

module top_mod (clk,rst,Flash_led,Run_led);
input clk;
input rst;
output Flash_led;
output [2:0]Run_led;
//---------------------------//
wire Flash_led;
flash_mod i1(.clk(clk),.rst(rst),.LED_OUT(Flash_led));
//---------------------------//
wire [2:0]Run_led;
run_mod i2(.clk(clk),.rst(rst),.LED_OUT(Run_led));

assign Flash_led =Flash_led;
assign Run_led =Run_led;
endmodule       

quartus 仿真没有错误 但是modelsim错误 ： ** Warning: (vsim-3009) [TSCALE] - Module 'flash_mod' does not have a `timescale directive in effect, but previous modules do.
#         Region: /waterlap_tb/i1/i1
# Loading work.run_mod
# ** Warning: (vsim-3009) [TSCALE] - Module 'run_mod' does not have a `timescale directive in effect, but previous modules do.
#         Region: /waterlap_tb/i1/i2
# WARNING: No extended dataflow License exists 此帖出自小平头技术问答