这是一个RAM，我是让它wr=1时是存入数据，wr=0时是读出数据，我用ModelSim-Altera仿真，可是输出是没有结果的，我还使用了一些其他方法都是没结果的，大家帮我看看问题出在哪里。
RAM代码：
`timescale 1ns/10ps
module RAM (clk,wr,addr,data_in,data_out);
  
  parameter WORDLENGTH=32;
  parameter ADDRLENGTH=4;
  
  input  clk,wr;
  input  [ADDRLENGTH-1:0] addr;
  input  [WORDLENGTH-1:0] data_in;
  output [WORDLENGTH-1:0] data_out;
  reg    [WORDLENGTH-1:0] data_out;
  
  reg    [WORDLENGTH-1:0] MEM [(1<<ADDRLENGTH)-1:0];
  
  always @ (posedge clk)
  begin
    if (wr) MEM[addr]<=data_in;
    else    data_out<=MEM[addr];
  end
endmodule

TESTBENCH:
`timescale 1ns/10ps
module RAM_tb;
  
  parameter WORDLENGTH=32;
  parameter ADDRLENGTH=10;
  
  reg  clk,wr;
  reg  [ADDRLENGTH-1:0] addr;
  reg  [WORDLENGTH-1:0] data_in;
  wire  [WORDLENGTH-1:0] data_out;
  
  initial clk=0;
  initial wr=1;
  initial addr=0;
  always #10 clk=~clk;
  always@(posedge clk )
  begin
    addr<=addr+1;
  end
  always @ (posedge clk) data_in={$random}%256;
  
  RAM M(.clk(clk),.wr(wr),.addr(addr),.data_in(data_in),.data_out(data_out));
  RAM N(.clk(clk),.wr(!wr),.addr(addr),.data_in(data_in),.data_out(data_out));
endmodule

下面是出来飞仿真波形： 此帖出自小平头技术问答