<font face="微软雅黑"><font style="font-size:18px">为什么RST信号下降沿之后y1和y2的值均没有变化，而是在clk上升沿才有变化？</font></font><br> <br> <br> <font color="#333333"><font face="微软雅黑"><font style="font-size:18px">veriloG代码如下</font></font></font><br> <br><p><br></p><pre style="max-width: 100%;"><code class="cpp hljs" codemark="1"><span class="hljs-function">module <span class="hljs-title">Blocking</span><span class="hljs-params">(y1,y2,clk,rst)</span></span>; output y1,y2; input clk,rst; reg y1,y2; always @(posedge clk or posedge rst) <span class="hljs-function">begin <span class="hljs-title">IF</span><span class="hljs-params">(rst)</span>y1</span>=<span class="hljs-number">0</span>; <span class="hljs-keyword">else</span> y1=y2; end always @(posedge clk or posedge rst) <span class="hljs-function">begin <span class="hljs-title">if</span><span class="hljs-params">(rst)</span>y2</span>=<span class="hljs-number">1</span>; <span class="hljs-keyword">else</span> y2=y1; end endmodule</code></pre> <br> <br> <font color="#333333"><font face="微软雅黑"><font style="font-size:18px">仿真波形如下</font></font></font><br> <font color="#333333"><font face="微软雅黑"><font style="font-size:18px"><br> <br> </font></font></font><br> <ignore_js_op> <dl class="tattl attm"> <dd> <img src="data/attach/1911/c3a0hpdtfesp88an1avawkgvoi6a51r3.png" alt="VEVS2CB])1Y}D7FZ4)S__VS.png" title="VEVS2CB])1Y}D7FZ4)S__VS.png"> </dd> </dl> </ignore_js_op> <p><br></p>