<font color="#333333"><font face="微软雅黑"><font style="font-size:18px">我遇到的错误：</font></font></font><br> <font face="微软雅黑"><font style="font-size:18px">Error (12006): Node instance "count" instantiates undefined entity "vDFF". Ensure that required library paths are specIFied correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.</font></font><br> <font color="#333333"><font face="微软雅黑"><font style="font-size:18px">----------------------------------------------------------------------------------</font></font></font><br> <br> <font color="#333333"><font face="微软雅黑"><font style="font-size:18px">我的源程序：gg.vhd文件如下</font></font></font><p><br></p><pre style="max-width: 100%;"><code class="cpp hljs" codemark="1">ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.ff.all; <span class="hljs-function">entity gg is <span class="hljs-title">generic</span><span class="hljs-params">( n: integer := <span class="hljs-number">4</span> )</span></span>; port( clk, rst: in std_logic; output: <span class="hljs-function">buffer <span class="hljs-title">std_logic_vector</span><span class="hljs-params">(n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span>)</span> )</span>; end gg; architecture impl of gg is signal nxt: std_logic_vector(n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span>); begin nxt &lt;= (others=&gt;<span class="hljs-string">'0'</span>) when rst <span class="hljs-keyword">else</span> output+<span class="hljs-number">1</span>; count: <span class="hljs-function">vDFF generic <span class="hljs-title">map</span><span class="hljs-params">(n)</span> port <span class="hljs-title">map</span><span class="hljs-params">(clk, nxt, output)</span></span>; end impl; </code></pre><p> <font face="微软雅黑"><font style="font-size:18px">我的package：</font></font>ff.vhd文件如下</p><p><br></p><pre style="max-width: 100%;"><code class="cpp hljs" codemark="1">library ieee; package ff is use ieee.std_logic_1164.all; <span class="hljs-function">component vDFF is <span class="hljs-title">generic</span><span class="hljs-params">( n: integer := <span class="hljs-number">1</span> )</span></span>; -- <span class="hljs-function">width <span class="hljs-title">port</span><span class="hljs-params">( clk: in std_logic; D: in std_logic_vector( n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span> )</span></span>; Q: <span class="hljs-function">out <span class="hljs-title">std_logic_vector</span><span class="hljs-params">( n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span> )</span> )</span>; end component; end package; library ieee; use ieee.std_logic_1164.all; <span class="hljs-function">entity vDFF is <span class="hljs-title">generic</span><span class="hljs-params">( n: integer := <span class="hljs-number">1</span> )</span></span>; port( clk: in std_logic; D: <span class="hljs-function">in <span class="hljs-title">std_logic_vector</span><span class="hljs-params">( n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span> )</span></span>; Q: <span class="hljs-function">out <span class="hljs-title">std_logic_vector</span><span class="hljs-params">( n<span class="hljs-number">-1</span> downto <span class="hljs-number">0</span> )</span> )</span>; end vDFF; <span class="hljs-function">architecture impl of vDFF is begin <span class="hljs-title">process</span><span class="hljs-params">(clk)</span> begin <span class="hljs-keyword">if</span> <span class="hljs-title">rising_edge</span><span class="hljs-params">(clk)</span> then Q &lt;</span>= D; end <span class="hljs-keyword">if</span>; end process; end impl; </code></pre> <font face="微软雅黑"><br> <font style="font-size:18px">-------------------------------------------------------------------</font><br> 我将ff.vhd 放在了quartus的安装目录下。<br> 每次仿真都出现同样错误，我需要调整我的代码，还是quartus的设置。<br> <br> <br> </font><br> <br> <br> <p><br></p><p></p><p><br></p>