<br> <pre style="max-width: 100%;"><code class="cpp hljs" codemark="1"> input clka, ); reg wea=<span class="hljs-number">0</span>; wire[<span class="hljs-number">15</span>:<span class="hljs-number">0</span>]doutb; always@(posedge clka) always@(posedge clka) begin addra&lt;=addra+<span class="hljs-number">1</span>; end wea&lt;=<span class="hljs-number">0</span>; IF(cnt&gt;=<span class="hljs-number">1034</span>) addrb&lt;=addrb+<span class="hljs-number">1</span>; .clka(clka), <span class="hljs-comment">// input wire clka</span> .addra(addra), <span class="hljs-comment">// input wire [9 : 0] addra</span> .clkb(clkb), <span class="hljs-comment">// input wire clkb</span> .doutb(doutb) <span class="hljs-comment">// output wire [15 : 0] doutb</span> endmodule 测试文件 <span class="hljs-function">module <span class="hljs-title">sim_RAM</span><span class="hljs-params">( )</span></span>; reg clka; reg clkb; <span class="hljs-comment">//调用RAM模块</span> <span class="hljs-function">RAM <span class="hljs-title">RAM_inst</span><span class="hljs-params">( .clka(clka)</span>, .<span class="hljs-title">clkb</span><span class="hljs-params">(clkb)</span> )</span>; initial begin clka=<span class="hljs-number">1</span>; clkb=<span class="hljs-number">1</span>; end always <span class="hljs-meta">#10 clka=~clka;</span> always <span class="hljs-meta">#20 clkb=~clkb;</span> endmodule</code></pre> <br> <p><br></p>