大家好，我最近在学习FPGA，用quartus11.1调用modelsim-altera10.0c仿真不出波形,quartus里面需要设置的都设置好了，并且跟网上下的资料做了多次对比，觉得设置没问题。用quartus11.1调用modelsim-altera10.0c，仿真不出波形仿真的结果图如图 未命名.jpg所示。VHDL程序如下所示：LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fp10 IS
    PORT(
         CLKJ:IN STD_LOGIC;
         CLKO:OUT STD_LOGIC
        );
END; ARCHITECTURE BEHAV OF fp10 IS SIGNAL  CNT:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLKJ) BEGIN IF CLKJ'EVENT AND CLKJ='1' THEN
 IF CNT < 9 THEN
  CNT <= CNT + 1;
 ELSE
  CNT <= (OTHERS =>'0');
  END IF;
END IF; IF CNT<5 THEN CLKO <= '0';
ELSE CLKO <= '1';
END IF; END PROCESS;
END BEHAV;   VHDL程序没有问题。因为我单独用modelsim-altera仿过。   我自己根据quartus生成的testbench文件改写的.vht文件如下： LIBRARY ieee;                                              
USE ieee.std_logic_1164.all;                               
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fp10_vhd_tst IS
END fp10_vhd_tst;
ARCHITECTURE fp10_arch OF fp10_vhd_tst IS
COMPONENT fp10
 PORT (
 CLKJ : IN STD_LOGIC;
 CLKO : OUT STD_LOGIC
 );
END COMPONENT;
SIGNAL CLKJ : STD_LOGIC := '0';
SIGNAL CLKO : STD_LOGIC;
constant clk_period: time := 20 ns;
BEGIN
 i1 : fp10
 PORT MAP (
 CLKJ => CLKJ,
 CLKO => CLKO
 );
                                 
always : PROCESS                                              
 BEGIN                                                         
       CLKJ <= '1';
    wait for clk_period/2;
    CLKJ <= '0';
    wait for clk_period/2;                                                          
END PROCESS always;                                         
END fp10_arch;
不知道什么问题，请大家帮我看一下，谢谢！ 顺便发一下quartus里面需要设置的图片。   此帖出自小平头技术问答