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Freescale OSBDM JM60仿真器OSBDM Development Port Interfaces
BGND Interface
The BGND interface provides the standard 6 pin connection for the single wire BGND signal type development port.Target types that apply this development port are the 9S08, RS08, and Coldfire V1.+V_TRG, TBGND, TRG_RST*, and Ground are applied by this port type.The BGND interface applies U4 as the signal transceiver.U4 is a 74LVC1T45 logic gate with voltage level shifting features.Operation on the target side (+V_TRG) is 1.8V to 5.5V.The JM60 side is always +5V from the +5V_SW signal.
JM60 signals TBGND_EN, TBGND_IN, and TBGND_OUT provide the communication and control for this interface.
All these signals are associated with JM60 timer channels for precise timing capability to a 41.67ns time step period.For more information on the input and output ports, refer to the Signal Chart section.
TBGND_ EN provides directional control for transmit or receive operations.The signal is logic high for transmit output and logic low to receive input.JM60 timer 2 channel 1 provides the primary signal direction control during the communication with the target.The idle condition is low so that the interface is not driven unless the communication is intended.During the communication, the direction is fixed to output the command to the target.During the reception, the signal is timed in edge aligned PWM mode to provide the BGND start pulse prior to the target reply input.
TBGND_OUT provides the transmit signal output from the JM60 to the target.Timer 2 channel 0 controls this signal in edge aligned PWM mode.For data transmission, the timer channel will output an active low signal with a time period that represents a logic one bit value or logic 0 bit value.In receive mode, the timer channel will provide a low output for the start bit on the BGND signal and then provide timing internally for the reply signal input time window.
TBGND_IN provides receive signal input from the target to the JM60.Timer 1 channel 3 is applied to measure the input signal duration in capture mode (25Mhz BDC clock maximum).This operation provides the timing to determine a logic 1 or 0 bit value input from the target.RS08 type targets apply a lower speed communication technique that inputs the JM60 port value (sample mode) instead of using the timer capture.This is due to the RS08 will not provide a stable input signal after the start bit generation and creates false timer capture edges.Other undefined target types may exhibit the same issue and may apply sample mode, if required (10MHz BDC clock maximum).NOTE The TBGND_OUT and TBGND_IN signals are connected with resistor R1. R1 provides isolation between the 2 timer channels.

sw离线烧录，留名，有时间自己整一个，通用的离线烧录器局限性太多！

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本帖最后由 abbott.yang 于 2015-8-21 16:19 编辑

shangdawei 发表于 2015-8-21 14:37
通过 SWD 控制target的flash寄存器达到同样的效果和
通过SWD下载程序到内部RAM来控制target的flash寄存器 ...

区别很小吧，特别是SWD速度够快的时候。blackmagic和DAP不同，它是用SWD直接操作target flash寄存器来完成的。
IO模拟速度慢，然后考虑的是做这个脱机烧录只是我要做的东西的一部分，后面会把整个产线的一些功能都集成进来，所以在启动时一次性把程序下进去完事。操作flash就可以少用几个SWD读写动作。
省点点时间，蚊子小也有肉。以前用资源，时钟很少很慢的低级MCU留下的习惯，比较抠门！

czdavid 发表于 2015-8-21 14:47
最简单和直接的就是直接SWD挂AHB总线控制target的FLASH寄存器。
当然为了效率和稳定性最好通过RAM缓冲。
...

David童鞋你的东西做好了没。。。。
我还想向你请教来着。就是积分低啊，不能发消息不能加好友！
万恶的积分！！！！