大虾们好!
俺们菜鸟,下面的例化引用好像有问题,请救救俺们吧
reg clkb,rdb,wrb;
reg [11:0]datab;
wire[11:0]qb;
assign qb = ( channelout == 0 ) ? q0 : (( channelout == 1 ) ? q1 : (( channelout == 2 ) ? q2 :(( channelout == 3 ) ? q3 : 12'bzzzz_zzzz_zzzz)));
assign data0 = ( channelout == 0 ) ? datab : 12'bzzzz_zzzz_zzzz;
assign rd0 = ( channelout == 0 ) ? rdb : 1'bz;
assign wr0 = ( channelout == 0 ) ? wrb : 1'bz;
assign clk0 = ( channelout == 0 ) ? clkb : 1'bz;
assign data1 = ( channelout == 1 ) ? datab : 12'bzzzz_zzzz_zzzz;
assign rd1 = ( channelout == 1 ) ? rdb : 1'bz;
assign wr1 = ( channelout == 1 ) ? wrb : 1'bz;
assign clk1 = ( channelout == 1 ) ? clkb : 1'bz;
assign data2 = ( channelout == 2 ) ? datab : 12'bzzzz_zzzz_zzzz;
assign rd2 = ( channelout == 2 ) ? rdb : 1'bz;
assign wr2 = ( channelout == 2 ) ? wrb : 1'bz;
assign clk2 = ( channelout == 2 ) ? clkb : 1'bz;
assign data3 = ( channelout == 3 ) ? datab : 12'bzzzz_zzzz_zzzz;
assign rd3 = ( channelout == 3 ) ? rdb : 1'bz;
assign wr3 = ( channelout == 3 ) ? wrb : 1'bz;
assign clk3 = ( channelout == 3 ) ? clkb : 1'bz;
wire [11:0]data0;
wire[11:0]q0;
wire rd0,wr0,clk0;
lpm_fifo0 fifo0(
.clock(clk0),
.data(data0),
.rdreq(rd0),
.wrreq(wr0),
.q(q0)
);
wire[11:0]data1;
wire[11:0]q1;
wire rd1,wr1,clk1;
lpm_fifo0 fifo1(
.clock(clk1),
.data(data1),
.rdreq(rd1),
.wrreq(wr1),
.q(q1)
);
wire[11:0]data2;
wire[11:0]q2;
wire rd2,wr2,clk2;
lpm_fifo0 fifo2(
.clock(clk2),
.data(data2),
.rdreq(rd2),
.wrreq(wr2),
.q(q2)
);
wire[11:0]data3;
wire[11:0]q3;
wire rd3,wr3,clk3;
lpm_fifo0 fifo3(
.clock(clk3),
.data(data3),
.rdreq(rd3),
.wrreq(wr3),
.q(q3)
);
此帖出自
小平头技术问答
help!!!
mayday!
mayday!!
提点意见:
1. 整体写法有点乱。
2. 例化FIFO端口的信号都应该是寄存器,最好不用WIRE。
3. 所有信号遵循先定义后使用。
4. 在例化过程中,不能插入定义WIRE语句。
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