library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shift1 is
    Port ( d : in  std_logic;
           a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s : in  STD_LOGIC;
                          
           q : out  STD_LOGIC);
end shift1;

architecture Behavioral of shift1 is
begin
a0:process(a,b,s)
variable clk:std_logic;
variable clk1:std_logic;
variable temp:std_logic;
begin
if(s='0')then
clk:=a;
clk1:=not a;
elsif(s='1')then
clk:=b;
clk1:=not b;
end if;
if(clk'event and clk='1')then
temp:=d;
end if;
if(clk1'event and clk1='1')then
q<=temp;
end if;
end process a0; 此帖出自小平头技术问答