module sw_debounce(clk,res_n,sw1_n,sw2_n,sw3_n,led1_n,led2_n,led3_n);
  input clk,res_n;           
  input sw1_n,sw2_n,sw3_n;    
  output led1_n,led2_n,led3_n;
reg[2:0] key_res;           
   always @(posedge clk or negedge res_n) 
     if(!res_n) key_res<=3'b111;
     else key_res<={sw3_n,sw2_n,sw1_n};
reg[2:0] key_res_r;        
    always @(posedge clk or negedge res_n)
       if(!res_n) key_res_r<=3'b111;
       else key_res_r<=key_res;    
wire [2:0] key_an=key_res_r&(~key_res);
reg [19:0] cnt;
    always @(posedge clk or negedge res_n)
    if(!res_n) cnt<=20'd0;
    else if(key_an) cnt<=20'd0;
    else cnt<=cnt+1'b1;
reg[2:0] low_sw;
   always @(posedge clk or negedge res_n)
    if(!res_n) low_sw<=3'b111;
    else if(cnt==20'hfffff) low_sw<={sw3_n,sw2_n,sw1_n};
reg[2:0] low_sw_r;
  always @(posedge clk or negedge res_n)
   if(!res_n) low_sw_r<=3'b111;
   else  low_sw_r<=low_sw;  
  wire[2:0] led_ctrl=low_sw_r&(~low_sw);
  reg d1,d2,d3;
  always @(posedge clk or negedge res_n)
  if(!res_n)
   begin
    d1<=0;
    d2<=0;
    d3<=0;
   end
  else
      begin       
      if(led_ctrl[0])d1<=~d1;
      if(led_ctrl[1])d2<=~d2;
      if(led_ctrl[2])d3<=~d3;
      end
assign led3=d1;
assign led2=d2;
assign led1=d3;  
endmodule     //`timescale 1ns/1ns
//`include "sw_debounce.v "
module sw_debounce_tb;
  reg sw1,sw2,sw3;
  reg clk;
  reg res;
  wire led1,led2,led3;
  initial
    begin
       clk=0;
       res=0;
       #100 res=1;
       #100 res=0;
       #100 res=1;
    end
  initial
   begin
     sw1=0;sw2=0;sw3=0;
     #100 sw1=0;sw2=0;sw3=1;
     #100 sw1=0;sw2=1;sw3=0;
     #100 sw1=0;sw2=1;sw3=1;
     #100 sw1=1;sw2=0;sw3=0;
     #100 sw1=1;sw2=0;sw3=1;
     #100 sw1=1;sw2=1;sw3=0;
     #100 sw1=1;sw2=1;sw3=1;
     #10000 $stop;
   end
  always #20 clk=~clk;
  sw_debounce sw_debounce_tb(clk,res,sw1,sw2,sw3,led1,led2,led3);
endmodule 为什么仿真的时候没有输出呢？哪位高手指点一下！谢谢！ 此帖出自小平头技术问答